Kaustav Banerjee
Kaustav Banerjee
UC Santa Barbara, Stanford University, UC Berkeley
E-mail confirmado em ece.ucsb.edu - Página inicial
Citado por
Citado por
3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
K Banerjee, SJ Souri, P Kapur, KC Saraswat
Proceedings of the IEEE 89 (5), 602-633, 2001
Electrical contacts to two-dimensional semiconductors
A Allain, J Kang, K Banerjee, A Kis
Nature materials 14 (12), 1195-1205, 2015
Role of Metal Contacts in Designing High-Performance Monolayer n-Type WSe2 Field Effect Transistors
W Liu, J Kang, D Sarkar, Y Khatami, D Jena, K Banerjee
Nano letters 13 (5), 1983-1990, 2013
Interconnect limits on gigascale integration (GSI) in the 21st century
JA Davis, R Venkatesan, A Kaloyeros, M Beylansky, SJ Souri, K Banerjee, ...
Proceedings of the IEEE 89 (3), 305-324, 2001
MoS2 Field-Effect Transistor for Next-Generation Label-Free Biosensors
D Sarkar, W Liu, X Xie, AC Anselmo, S Mitragotri, K Banerjee
ACS nano 8 (4), 3992-4003, 2014
A subthermionic tunnel field-effect transistor with an atomically thin channel
D Sarkar, X Xie, W Liu, W Cao, J Kang, Y Gong, S Kraemer, PM Ajayan, ...
Nature 526 (7571), 91-95, 2015
Computational study of metal contacts to monolayer transition-metal dichalcogenide semiconductors
J Kang, W Liu, D Sarkar, D Jena, K Banerjee
Physical Review X 4 (3), 031005, 2014
Carbon nanomaterials for next-generation interconnects and passives: physics, status, and prospects
H Li, C Xu, N Srivastava, K Banerjee
IEEE Transactions on electron devices 56 (9), 1799-1821, 2009
A power-optimal repeater insertion methodology for global interconnects in nanometer designs
K Banerjee, A Mehrotra
IEEE Transactions on Electron Devices 49 (11), 2001-2007, 2002
Circuit modeling and performance analysis of multi-walled carbon nanotube interconnects
H Li, WY Yin, K Banerjee, JF Mao
IEEE Transactions on electron devices 55 (6), 1328-1337, 2008
Modeling, analysis, and design of graphene nano-ribbon interconnects
C Xu, H Li, K Banerjee
IEEE transactions on electron devices 56 (8), 1567-1578, 2009
Performance analysis of carbon nanotube interconnects for VLSI applications
N Srivastava, K Banerjee
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
Synthesis of high-quality monolayer and bilayer graphene on copper using chemical vapor deposition
W Liu, H Li, C Xu, Y Khatami, K Banerjee
Carbon 49 (13), 4122-4130, 2011
Vertical Si-Nanowire-Type Tunneling FETs With Low Subthreshold Swing () at Room Temperature
R Gandhi, Z Chen, N Singh, K Banerjee, S Lee
IEEE Electron Device Letters 32 (4), 437-439, 2011
High-performance MoS2 transistors with low-resistance molybdenum contacts
J Kang, W Liu, K Banerjee
Applied Physics Letters 104 (9), 093106, 2014
Steep subthreshold slope n-and p-type tunnel-FET devices for low-power and energy-efficient digital circuits
Y Khatami, K Banerjee
IEEE Transactions on Electron Devices 56 (11), 2752-2761, 2009
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
AH Ajami, K Banerjee, M Pedram
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005
Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs
C Xu, H Li, R Suaya, K Banerjee
IEEE Transactions on Electron Devices 57 (12), 3405-3417, 2010
Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs
S Im, K Banerjee
International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No …, 2000
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
GL Loi, B Agrawal, N Srivastava, SC Lin, T Sherwood, K Banerjee
Proceedings of the 43rd annual Design Automation Conference, 991-996, 2006
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