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Cesar Albenes Zeferino
Cesar Albenes Zeferino
Professor of Computer Science, University of Vale do Itajaí
E-mail confirmado em univali.br
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SoCIN: a parametric and scalable network-on-chip
CA Zeferino, AA Susin
16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003 …, 2003
3522003
SPIN: a scalable, packet switched, on-chip micro-network
A Adriahantenaina, H Charlery, A Greiner, L Mortiez, CA Zeferino
2003 Design, Automation and Test in Europe Conference and Exhibition, 70-73 …, 2003
3202003
RASoC: A router soft-core for networks-on-chip
CA Zeferino, ME Kreutz, AA Susin
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
1572004
A study on communication issues for systems-on-chip
CA Zeferino, ME Kreutz, L Carro, AA Susin
Proceedings. 15th Symposium on Integrated Circuits and Systems Design, 121-126, 2002
1372002
The impact of NoC reuse on the testing of core-based systems
É Cota, M Kreutz, CA Zeferino, L Carro, M Lubaszewski, A Susin
Proceedings. 21st VLSI Test Symposium, 2003., 128-133, 2003
1182003
Paris: a parameterizable interconnect switch for networks-on-chip
CA Zeferino, FGME Santo, AA Susin
Proceedings of the 17th symposium on Integrated circuits and system design …, 2004
562004
Redes-em-Chip: arquiteturas e modelos para avaliação de área e desempenho
CA Zeferino
532003
Communication architectures for system-on-chip
ME Kreutz, L Carro, CA Zeferino, AA Susin
Symposium on Integrated Circuits and Systems Design, 14-19, 2001
322001
A solution for dynamic management of user profiles in IoT environments
V Leithardt, D Santos, L Silva, F Viel, C Zeferino, J Silva
IEEE Latin America Transactions 18 (07), 1193-1199, 2020
292020
Security mechanisms to improve the availability of a network-on-chip
S Baron, MS Wangham, CA Zeferino
2013 IEEE 20th International Conference on Electronics, Circuits, and …, 2013
262013
A review of techniques for implementing elliptic curve point multiplication on hardware
A Verri Lucca, GA Mariano Sborz, VRQ Leithardt, M Beko, ...
Journal of Sensor and Actuator Networks 10 (1), 3, 2020
242020
Bipide–ambiente de desenvolvimento integrado para a arquitetura dos processadores BIP
PV Vieira, ALA Raabe, CA Zeferino
Revista Brasileira de Informática na Educação 18 (01), 32, 2010
192010
An Efficient Interface for the Integration of IoT Devices with Smart Grids
F Viel, L Augusto Silva, VRQ Leithardt, JF De Paz Santana, ...
Sensors 20 (10), 2849, 2020
182020
Processadores para ensino de conceitos básicos de arquitetura de computadores
D Morandi, ALA Raabe, CA Zeferino
Workshop sobre Educação em Arquitetura de Computadores-WEAC 2006, 17-24, 2006
162006
A basic processor for teaching digital circuits and systems design with FPGA
MC Pereira, PV Viera, ALA Raabe, CA Zeferino
2012 VIII Southern Conference on Programmable Logic, 1-6, 2012
152012
Um processador básico para o ensino de conceitos de arquitetura e organização de computadores
D Morandi, MC Pereira, ALA Raabe, CA Zeferino
Hífen, Uruguaiana 30, 73-80, 2006
152006
Um enfoque interdisciplinar no ensino de arquitetura de computadores
CA Zeferino, ALA Raabe, PV Vieira, MC Pereira, C Martins, P Navaux, ...
C. Martins, P. Navaux, R. Azevedo, S. Kofuji. Arquitetura de Computadores …, 2012
142012
Deadline, energy and buffer-aware task mapping optimization in NoC-based SoCs using genetic algorithms
JV Bruch, EA Da Silva, CA Zeferino, LS Indrusiak
2017 VII Brazilian Symposium on Computing Systems Engineering (SBESC), 86-93, 2017
132017
Adding mechanisms for QoS to a network-on-chip
MD Berejuck, CA Zeferino
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System …, 2009
132009
ParlS: A parameterizable interconnect switch for Networks-on-Chips
C Albenes, ZFGME Santo, AA Susin
Proc. ACM Conference, 204-209, 2004
122004
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