Cesar Albenes Zeferino
Cesar Albenes Zeferino
Professor of Computer Science, University of Vale do Itajaí
Verified email at univali.br
Title
Cited by
Cited by
Year
SoCIN: a parametric and scalable network-on-chip
CA Zeferino, AA Susin
16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003 …, 2003
3442003
SPIN: a scalable, packet switched, on-chip micro-network
A Adriahantenaina, H Charlery, A Greiner, L Mortiez, CA Zeferino
2003 Design, Automation and Test in Europe Conference and Exhibition, 70-73 …, 2003
3212003
RASoC: A router soft-core for networks-on-chip
CA Zeferino, ME Kreutz, AA Susin
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
1572004
A study on communication issues for systems-on-chip
CA Zeferino, ME Kreutz, L Carro, AA Susin
Proceedings. 15th Symposium on Integrated Circuits and Systems Design, 121-126, 2002
1372002
The impact of NoC reuse on the testing of core-based systems
É Cota, M Kreutz, CA Zeferino, L Carro, M Lubaszewski, A Susin
Proceedings. 21st VLSI Test Symposium, 2003., 128-133, 2003
1202003
Paris: a parameterizable interconnect switch for networks-on-chip
CA Zeferino, FGME Santo, AA Susin
Proceedings of the 17th symposium on Integrated circuits and system design …, 2004
572004
Redes-em-Chip: arquiteturas e modelos para avaliação de área e desempenho
CA Zeferino
462003
Communication architectures for system-on-chip
ME Kreutz, L Carro, CA Zeferino, AA Susin
Symposium on Integrated Circuits and Systems Design, 14-19, 2001
322001
Security mechanisms to improve the availability of a network-on-chip
S Baron, MS Wangham, CA Zeferino
2013 IEEE 20th International Conference on Electronics, Circuits, and …, 2013
222013
A solution for dynamic management of user profiles in IoT environments
V Leithardt, D Santos, L Silva, F Viel, C Zeferino, J Silva
IEEE Latin America Transactions 18 (07), 1193-1199, 2020
172020
Bipide–ambiente de desenvolvimento integrado para a arquitetura dos processadores BIP
PV Vieira, ALA Raabe, CA Zeferino
Revista Brasileira de Informática na Educação 18 (01), 32, 2010
172010
Processadores para ensino de conceitos básicos de arquitetura de computadores
D Morandi, ALA Raabe, CA Zeferino
Proceedings of the 18th International Symposium on Computer Architecture and …, 2006
162006
A basic processor for teaching digital circuits and systems design with FPGA
MC Pereira, PV Viera, ALA Raabe, CA Zeferino
2012 VIII Southern Conference on Programmable Logic, 1-6, 2012
142012
Adding mechanisms for QoS to a network-on-chip
MD Berejuck, CA Zeferino
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System …, 2009
132009
Um processador básico para o ensino de conceitos de arquitetura e organização de computadores
D Morandi, MC Pereira, ALA Raabe, CA Zeferino
Hífen, Uruguaiana 30, 73-80, 2006
132006
Um enfoque interdisciplinar no ensino de arquitetura de computadores
CA Zeferino, ALA Raabe, PV Vieira, MC Pereira, C Martins, P Navaux, ...
C. Martins, P. Navaux, R. Azevedo, S. Kofuji. Arquitetura de Computadores …, 2012
122012
ParlS: A parameterizable interconnect switch for Networks-on-Chips
C Albenes, ZFGME Santo, AA Susin
Proc. ACM Conference, 204-209, 2004
122004
BrownPepper: A SystemC-based simulator for performance evaluation of Networks-on-Chip
JV Bruch, MR Pizzoni, CA Zeferino
2009 17th IFIP International Conference on Very Large Scale Integration …, 2009
112009
Introdução à programação e à implementação de processadores por estudantes do ensino médio
F Viel, A Raabe, C Zeferino
Anais do Workshop de Informática na Escola 20 (1), 248, 2014
102014
Deadline, energy and buffer-aware task mapping optimization in NoC-based SoCs using genetic algorithms
JV Bruch, EA Da Silva, CA Zeferino, LS Indrusiak
2017 VII Brazilian Symposium on Computing Systems Engineering (SBESC), 86-93, 2017
92017
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Articles 1–20