| Germanium MOSFET devices: Advances in materials understanding, process development, and electrical performance DP Brunco, B De Jaeger, G Eneman, J Mitard, G Hellings, A Satta, ... Journal of The Electrochemical Society 155 (7), H552, 2008 | 341 | 2008 |
| High performance Ge pMOS devices using a Si-compatible process flow P Zimmerman, G Nicholas, B De Jaeger, B Kaczer, A Stesmans, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 174 | 2006 |
| Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability J Mitard, B De Jaeger, FE Leys, G Hellings, K Martens, G Eneman, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 145 | 2008 |
| Optimisation of a thin epitaxial Si layer as Ge passivation layer to demonstrate deep sub-micron n-and p-FETs on Ge-On-Insulator substrates B De Jaeger, R Bonzom, F Leys, O Richard, J Van Steenbergen, ... Microelectronic engineering 80, 26-29, 2005 | 140 | 2005 |
| Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography MJH Van Dal, N Collaert, G Doornbos, G Vellianitis, G Curatola, ... 2007 IEEE symposium on VLSI technology, 110-111, 2007 | 111 | 2007 |
| Impact of EOT scaling down to 0.85 nm on 70nm Ge-pFETs technology with STI J Mitard, C Shea, B DeJaeger, A Pristera, G Wang, M Houssa, G Eneman, ... 2009 Symposium on VLSI Technology, 82-83, 2009 | 70 | 2009 |
| Thin epitaxial Si films as a passivation method for Ge (1 0 0): Influence of deposition temperature on Ge surface segregation and the high-k/Ge interface quality FE Leys, R Bonzom, B Kaczer, T Janssens, W Vandervorst, B De Jaeger, ... Materials science in semiconductor processing 9 (4-5), 679-684, 2006 | 67 | 2006 |
| 25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/in the source and drain regions P Verheyen, N Collaert, R Rooyackers, R Loo, D Shamiryan, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 194-195, 2005 | 66 | 2005 |
| The influence of the epitaxial growth process parameters on layer characteristics and device performance in Si-passivated Ge pMOSFETs M Caymax, F Leys, J Mitard, K Martens, L Yang, G Pourtois, ... Journal of The Electrochemical Society 156 (12), H979, 2009 | 65 | 2009 |
| Germanium: The past and possibly a future material for microelectronics DP Brunco, B De Jaeger, G Eneman, A Satta, V Terzieva, L Souriau, ... ECS Transactions 11 (4), 479, 2007 | 57 | 2007 |
| Electrical and reliability characterization of metal-gate/HfO2/Ge FET’s with Si passivation B Kaczer, B De Jaeger, G Nicholas, K Martens, R Degraeve, M Houssa, ... Microelectronic engineering 84 (9-10), 2067-2070, 2007 | 45 | 2007 |
| Gatestacks for scalable high-performance FinFETs G Vellianitis, MJH Van Dal, L Witters, G Curatola, G Doornbos, N Collaert, ... 2007 IEEE International Electron Devices Meeting, 681-684, 2007 | 42 | 2007 |
| On the scalability of source/drain current enhancement in thin film sSOI E Augendre, G Eneman, A De Keersgieter, V Simons, I De Wolf, J Ramos, ... Proceedings of 35th European Solid-State Device Research Conference, 2005 …, 2005 | 42 | 2005 |
| Electronic energy spectrum of two-dimensional solids and a chain of C atoms from a quantum network model C Amovilli, FE Leys, NH March Journal of mathematical chemistry 36, 93-112, 2004 | 42 | 2004 |
| Method for doping semiconductor structures and the semiconductor device thereof R Loo, F Leys, M Caymax US Patent 8,507,337, 2013 | 37 | 2013 |
| Selective epitaxial growth of germanium on Si wafers with shallow trench isolation: an approach for Ge virtual substrates G Wang, FE Leys, L Souriau, R Loo, M Caymax, DP Brunco, J Geypen, ... ECS Transactions 16 (10), 829, 2008 | 37 | 2008 |
| Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth N Collaert, R Rooyackers, A Hikavyy, A Dixit, F Leys, P Verheyen, R Loo, ... Thin Solid Films 517 (1), 101-104, 2008 | 36 | 2008 |
| In situ phosphorus doping of germanium by APCVD G Dilliway, R Van Den Boom, A Moussa, F Leys, B Van Daele, ... ECS Transactions 3 (7), 599, 2006 | 36 | 2006 |
| Minimization of specific contact resistance in multiple gate NFETs by selective epitaxial growth of Si in the HDD regions A Dixit, KG Anil, R Rooyackers, F Leys, M Kaiser, N Collaert, K De Meyer, ... Solid-state electronics 50 (4), 587-593, 2006 | 32 | 2006 |
| Vapor phase doping with N-type dopant into silicon by atmospheric pressure chemical vapor deposition S Takeuchi, ND Nguyen, FE Leys, R Loo, T Conard, W Vandervorst, ... ECS Transactions 16 (10), 495, 2008 | 31 | 2008 |
