Jae Young Hur
Jae Young Hur
Y Computing, Inc.
Verified email at ycomputing.co.kr - Homepage
Title
Cited by
Cited by
Year
Hardwired Networks on Chip in FPGAs to Unify Functional and Configuration Interconnects
K Goossens, M Bennebroek, JY Hur, MA Wahlah
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 45-54, 2008
552008
FPGA implementation of parallel histogram computation
A Shahbahrami, JY Hur, B Juurlink, S Wong
2nd HiPEAC Workshop on Reconfigurable Computing, 63-72, 2008
282008
Systematic customization of on-chip crossbar interconnects
JY Hur, T Stefanov, S Wong, S Vassiliadis
International Workshop on Applied Reconfigurable Computing, 61-72, 2007
242007
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs
JY Hur, S Wong, S Vassiliadis
Lecture Notes in Computer Science 4419, 49-60, 2007
162007
System-on-chip and address translation method thereof using a translation lookaside buffer and a prefetch buffer
SM Hong, SJ Lee, JY Hur, JW Kwon, I Park, JJ Lee, JY Jung
US Patent 9,645,934, 2017
152017
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
JY Hur, T Stefanov, S Wong, K Goossens
IET computers & digital techniques 6 (1), 59-68, 2012
142012
Customizing reconfigurable on-chip crossbar scheduler
JY Hur, T Stefanov, S Wong, S Vassiliadis
2007 IEEE International Conf. on Application-specific Systems, Architectures …, 2007
122007
Parallel merge sort on a binary tree on-chip network
S Wong, S Vassiliadis, JY Hur
Proceedings of the 16th Annual Workshop on Circuits, Systems and Signal …, 2005
112005
METHOD AND APPARATUS FOR PERFORMING ADAPTIVE MEMORY BANK ADDRESSING
JY Hur, SW Rhim, BH Lee
US Patent 8,817,033, 2015
92015
System on chip for updating partial frame of image and method of operating the same
JH Roh, KM Kim, YM Song, JH Lee, JY Hur, SM Hong, BT Lee, KM Chun
US Patent App. 14/169,410, 2014
82014
A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices
T Marconi, JY Hur, K Bertels, G Gaydadjiev
2010 IEEE 8th Symposium on Application Specific Processors (SASP), 87-92, 2010
82010
Customizing and hardwiring on-chip interconnects in FPGAs
JY Hur
TU Delft, 2011
72011
Representing contiguity in page table for memory management units
JY Hur
IEEE Int’l Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC …, 2017
62017
Bus System Including ID Converter and Converting Method Thereof
BH Lee, SW Rhim, EC Lim, JY Hur
US Patent 9,021,169, 2015
62015
Partially reconfigurable point-to-point FPGA interconnects
JY Hur, S Wong, S Vassiliadis
International Journal of Electronics 95 (7), 725-742, 2008
52008
Contiguity Representation in Page Table for Memory Management Units
JY Hur
IEEE Transactions on Very Large Scale Integration Systems 27 (1), 147-158, 2019
42019
Address generator of image processing device and operating method of address generator
JY Hur
US Patent App. 13/785,907, 2013
42013
Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays
JY Hur, K Goossens, L Mhamdi, MA Wahlah
IET Computers & Digital Techniques 6 (6), 396-405, 2012
42012
Design trade-offs in customized on-chip crossbar schedulers
JY Hur, S Wong, T Stefanov
Journal of Signal Processing Systems 58 (1), 69-85, 2010
42010
Performance analysis of soft and hard single-hop and multi-hop circuit-switched interconnects for FPGAs
JY Hur, K Goossens, L Mhamdi
Proceedings of the IFIP International Conference on Very Large Scale …, 2008
42008
The system can't perform the operation now. Try again later.
Articles 1–20