| Energy-efficient SATD for beyond HEVC I Seidel, AB Bräscher, JL Güntzel, L Agostini 2016 IEEE international symposium on circuits and systems (ISCAS), 802-805, 2016 | 20 | 2016 |
| Energy-efficient Hadamard-based SATD architectures LH Cancellier, AB Bräscher, I Seidel, JL Güntzel Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 1-6, 2014 | 14 | 2014 |
| Combining pel decimation with partial distortion elimination to increase SAD energy efficiency I Seidel, AB Bräscher, JL Güntzel 2015 25th International Workshop on Power and Timing Modeling, Optimization …, 2015 | 13 | 2015 |
| Exploring optimized Hadamard methods to design energy-efficient SATD architectures LH Cancellier, AB Brascher, I Seidel, JL Güntzel, L Agostini Journal of Integrated Circuits and Systems 10 (2), 113-122, 2015 | 8 | 2015 |
| Improving the energy efficiency of a low-area SATD hardware architecture using fine grain PDE AB Bräscher, I Seidel, JL Güntzel Proceedings of the 30th Symposium on Integrated Circuits and Systems Design …, 2017 | 6 | 2017 |
| Exploring pel decimation to trade off between energy and quality in video coding I Seidel, AB Bräscher, M Monteiro, JL Güntzel 2014 IEEE 5th Latin American Symposium on Circuits and Systems, 1-4, 2014 | 6 | 2014 |
| On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation I Seidel, BG de Moraes, AB Bräscher, JL Güntzel 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013 | 6 | 2013 |
| Towards optimal use of pel decimation to trade off quality for energy I Seidel, AB Braescher, M Monteiro, JL Guentzel Analog Integrated Circuits and Signal Processing 85, 107-128, 2015 | 1 | 2015 |
| A New Approach to Video Coding Leveraging Hybrid Coding and Video Frame Interpolation AB Bräscher, GF Da Silveira, LH Cancellier, I Seidel, M Grellert, ... 2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems …, 2023 | | 2023 |
| Evaluation of motion estimation lagrange multipliers in HEVC AB Bräscher | | 2020 |
| Arquiteturas Energeticamente Eficientes para SATD com Tamanho de Bloco Variável no HEVC AB Bräscher Revista Abstração, 15, 2018 | | 2018 |
| Analysis of Pel Decimation and Technology Choices to Reduce Energy on SAD Calculation I Seidel, AB Bräscher, BG de Moraes, M Monteiro, JL Güntzel Journal of Integrated Circuits and Systems 9 (1), 48-59, 2014 | | 2014 |
| Comparison of 90nm and 65nm Logic Synthesis of a SAD Configurable VLSI Architecture I Seidel, BG de Moraes, AB Bräscher, JL Güntzel | | 2013 |
