Low-power near-threshold 10T SRAM bit cells with enhanced data-independent read port leakage for array augmentation in 32-nm CMOS S Gupta, K Gupta, BH Calhoun, N Pandey
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (3), 978-988, 2018
80 2018 A 32-nm subthreshold 7T SRAM bit cell with read assist S Gupta, K Gupta, N Pandey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (12 …, 2017
61 2017 Pentavariate Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read S Gupta, K Gupta, N Pandey
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (10), 3326-3337, 2018
41 2018 Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells K Gupta, N Pandey, M Gupta
Microelectronics Journal 44 (6), 561-567, 2013
39 2013 A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability P Sharma, S Gupta, K Gupta, N Pandey
Microelectronics Journal 97, 104703, 2020
34 2020 MCML D-latch using triple-tail cells: Analysis and design K Gupta, N Pandey, M Gupta
Active and Passive Electronic Components 2013, 2013
29 2013 An efficient triple-tail cell based PFSCL D latch N Pandey, K Gupta, M Gupta
Microelectronics Journal 45 (8), 1001-1007, 2014
17 2014 Low-voltage MOS current mode logic multiplexer K Gupta, N Pandey, M Gupta
Radioengineering Journal 22, 259-268, 2013
17 2013 Low-power tri-state buffer in MOS current mode logic K Gupta, N Pandey, M Gupta
Analog integrated circuits and signal processing 75, 157-160, 2013
17 2013 A novel active shunt-peaked MCML-based high speed four-bit ripple-carry adder K Gupta, N Pandey, M Gupta
2010 International Conference on Computer and Communication Technology …, 2010
16 2010 Model and design of improved current mode logic gates K Gupta, N Pandey, M Gupta
Springer Singapore, 2020
15 2020 An arithmetic and logical unit using reversible gates P Khatter, N Pandey, K Gupta
2018 International Conference on Computing, Power and Communication …, 2018
15 2018 PFSCL based linear feedback shift register A Tyagi, N Pandey, K Gupta
2016 international conference on computational techniques in information and …, 2016
15 2016 Low power D-latch design using MCML tri-state buffers N Pandey, K Gupta, M Gupta
2014 international conference on signal processing and integrated networks …, 2014
14 2014 Performance comparison of MCML and PFSCL gates in 0.18 μm CMOS technology K Gupta, R Sridhar, J Chaudhary, N Pandey, M Gupta
2011 2nd international conference on computer and communication technology …, 2011
12 2011 A novel PVT‐variation‐ tolerant Schmitt‐trigger‐based 12T SRAM cell with improved write ability and high ION /IOFF ratio in sub‐threshold region M Gupta, K Gupta, N Pandey
International Journal of Circuit Theory and Applications 49 (11), 3789-3810, 2021
11 2021 A data‐independent 9T SRAM cell with enhanced ION /IOFF ratio and RBL voltage swing in near threshold and sub‐threshold region M Gupta, K Gupta, N Pandey
International Journal of Circuit Theory and Applications 49 (4), 953-969, 2021
10 2021 Low voltage 7T SRAM cell in 32nm CMOS technology node B Rawat, K Gupta, N Goel
2018 international conference on computing, power and communication …, 2018
10 2018 DFAL based implementation of frequency divider-by-3 N Pandey, R Pandey, K Gupta
2015 Annual IEEE India Conference (INDICON), 1-6, 2015
10 2015 A novel low-power nonvolatile 8T1M SRAM cell D Singh, K Gupta, N Pandey
Arabian Journal for Science and Engineering 47 (3), 3163-3179, 2022
9 2022