Marcio Merino Fernandes
Marcio Merino Fernandes
UFSCar - Departamento de Computação
Verified email at dc.ufscar.br
Title
Cited by
Cited by
Year
Distributed modulo scheduling
MM Fernandes, J Llosa, N Topham
Proceedings Fifth International Symposium on High-Performance Computer …, 1999
541999
A Real Time Gesture Recognition System for Mobile Robots.
V Bonato, AK Sanches, MM Fernandes, JMP Cardoso, E do Valle Simões, ...
ICINCO (2), 207-214, 2004
462004
Using queues for register file organization in VLIW architectures
MM Fernandes, J Llosa, N Topham
University of Edinburgh, Department of Computer Science, Computer Systems Group, 1997
331997
Processors and compiling methods for processors
MM Fernandes, RM Livesley
US Patent 7,747,990, 2010
222010
Processors and compiling methods for processors
MM Fernandes, RM Livesley
US Patent 7,747,990, 2010
222010
Partitioned schedules for clustered vliw architectures
MM Fernandes, J Llosa, N Topham
Proceedings of the First Merged International Parallel Processing Symposium …, 1998
211998
ARCHITECT-R: a system for reconfigurable robots design
RA Gonçalves, PA Moraes, JMP Cardoso, DF Wolf, MM Fernandes, ...
Proceedings of the 2003 ACM symposium on Applied computing, 679-683, 2003
182003
A smart camera with gesture recognition and SLAM capabilities for mobile robots
V Bonato, MM Fernandes, E Marques
International journal of electronics 93 (6), 385-401, 2006
132006
LALP: a novel language to program custom FPGA-based architectures
R Menotti, JMP Cardoso, MM Fernandes, E Marques
2009 21st International Symposium on Computer Architecture and High …, 2009
122009
A clustered VLIW architecture based on queue register files
MM Fernandes
University of Edinburgh. College of Science and Engineering. School of …, 1998
121998
LALP: A language to program custom FPGA-based acceleration engines
R Menotti, JMP Cardoso, MM Fernandes, E Marques
International Journal of Parallel Programming 40 (3), 262-289, 2012
112012
A mersenne twister hardware implementation for the Monte Carlo localization algorithm
V Bonato, BF Mazzotti, MM Fernandes, E Marques
Journal of Signal Processing Systems 70 (1), 75-85, 2013
92013
Automatic generation of FPGA hardware accelerators using a domain specific language
R Menotti, JMP Cardoso, MM Fernandes, E Marques
2009 International Conference on Field Programmable Logic and Applications …, 2009
92009
Allocating lifetimes to queues in software pipelined architectures
MM Fernandes, J Llosa, N Topham
European Conference on Parallel Processing, 1066-1073, 1997
81997
Practical education fostered by research projects in an embedded systems course
V Bonato, MM Fernandes, JMP Cardoso, E Marques
International Journal of Reconfigurable Computing 2014, 2014
62014
On using LALP to map an audio encoder/decoder on FPGAs
R Menotti, JMP Cardoso, MM Fernandes, E Marques
2010 IEEE International Symposium on Industrial Electronics, 3063-3068, 2010
52010
Extending a VLIW architecture model
MM Fernandes, J Llosa, N Topham
University of Edinburgh, Computer Systems Group, 1998
51998
Reconfigurable Computing: Architectures, Tools and Applications: Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007, Proceedings
PC Diniz, E Marques, K Bertels, MM Fernandes, JMP Cardoso
Springer, 2007
42007
Teaching embedded systems with FPGAs throughout a computer science course
V Bonato, R Menotti, E Simões, MM Fernandes, E Marques
Proceedings of the 2004 workshop on Computer architecture education: held in …, 2004
42004
Processors and compiling methods for processors
MM Fernandes, RM Livesley
US Patent 8,677,330, 2014
32014
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