| High throughput FIR filter architectures using retiming and modified CSLA based adders P Patali, S Thottathikkulam Kassim IET Circuits, Devices & Systems 13 (7), 1007-1017, 2019 | 30 | 2019 |
| Efficient modular hybrid adders and Radix-4 booth multipliers for DSP applications P Patali, ST Kassim Microelectronics Journal 96, 104701, 2020 | 27 | 2020 |
| An efficient architecture for signed carry save multiplication P Patali, ST Kassim IEEE Letters of the Computer Society 3 (1), 9-12, 2020 | 14 | 2020 |
| High throughput and energy efficient FIR filter architectures using retiming and two level pipelining P Patali, ST Kassim Procedia Computer Science 171, 617-626, 2020 | 13 | 2020 |
| Delay and energy efficient modular hybrid adder for signal processor architectures P Pramod, TK Shahana IETE Journal of Research 68 (2), 924-934, 2022 | 11 | 2022 |
| High throughput and energy efficient linear phase FIR filter architectures P Patali, ST Kassim Microprocessors and Microsystems 87, 104367, 2021 | 9 | 2021 |
| High throughput adaptive filter architecture using modified transpose form FIR filters P Pramod, TK Shahana J. Adv. Res. Dyn. Control Syst 10 (15), 68-82, 2018 | 9 | 2018 |
| Exact and approximate multiplications for signal processing applications P Patali, ST Kassim Microelectronics Journal 132, 105688, 2023 | 7 | 2023 |
| Power and area efficient carry select adder UP Anagha, P Pramod 2015 IEEE Recent Advances in Intelligent Computational Systems (RAICS), 17-20, 2015 | 6 | 2015 |
| Pipelined convolution using Vedic multiplier K Pranav, P Pramod 2015 IEEE Recent Advances in Intelligent Computational Systems (RAICS), 33-38, 2015 | 3 | 2015 |
| Design of High Speed Low Power Counter using Pipelining KN Vijeyakumar, V Sumathy, P Pramod, S Saravanakumar NISCAIR-CSIR, India, 2014 | 1 | 2014 |
SHAHANA TKProfessor, School of Engineering, Cochin University of Science and TechnologyVerified email at cusat.ac.in
