| Efficient software-based online phase classification A Sembrant, D Eklov, E Hagersten 2011 IEEE International Symposium on Workload Characterization (IISWC), 104-115, 2011 | 63 | 2011 |
| Modeling performance variation due to cache sharing A Sandberg, A Sembrant, E Hagersten, D Black-Schaffer 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 58 | 2013 |
| Tlc: A tag-less cache for reducing dynamic first level cache energy A Sembrant, E Hagersten, D Black-Shaffer Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 50 | 2013 |
| Power-sleuth: A tool for investigating your program's power behavior V Spiliopoulos, A Sembrant, S Kaxiras 2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation …, 2012 | 47 | 2012 |
| Phase guided profiling for fast cache modeling A Sembrant, D Black-Schaffer, E Hagersten Proceedings of the Tenth International Symposium on Code Generation and …, 2012 | 38 | 2012 |
| Phase behavior in serial and parallel applications A Sembrant, D Black-Schaffer, E Hagersten 2012 IEEE International Symposium on Workload Characterization (IISWC), 47-58, 2012 | 36 | 2012 |
| Long term parking (ltp) criticality-aware resource allocation in ooo processors A Sembrant, T Carlson, E Hagersten, D Black-Shaffer, A Perais, A Seznec, ... Proceedings of the 48th International Symposium on Microarchitecture, 334-346, 2015 | 35 | 2015 |
| The Direct-to-Data (D2D) Cache: Navigating the Cache Hierarchy with a Single Lookup A Sembrant, E Hagersten, D Black-Schaffer Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on …, 2014 | 27 | 2014 |
| Management of shared pipeline resource usage based on level information E Hagersten, A Sembrant, D Black-schaffer, S Kaxiras US Patent 10,409,725, 2019 | 19 | 2019 |
| Cost-effective speculative scheduling in high performance processors A Perais, A Seznec, P Michaud, A Sembrant, E Hagersten ACM SIGARCH Computer Architecture News 43 (3S), 247-259, 2015 | 19 | 2015 |
| Systems and methods for implementing a tag-less shared cache and a larger backing cache E Hagersten, A Sembrant, D Black-schaffer, S Kaxiras US Patent 10,402,331, 2019 | 18 | 2019 |
| Systems and methods for reducing first level cache energy by eliminating cache address tags E Hagersten, A Sembrant, D Black-schaffer, S Kaxiras US Patent 10,671,543, 2020 | 15 | 2020 |
| A graphics tracing framework for exploring CPU+ GPU memory systems A Sembrant, TE Carlson, E Hagersten, D Black-Schaffer 2017 IEEE International Symposium on Workload Characterization (IISWC), 54-65, 2017 | 12 | 2017 |
| A split cache hierarchy for enabling data-oriented optimizations A Sembrant, E Hagersten, D Black-Schaffer 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 12 | 2017 |
| Systems and methods for direct data access in multi-level cache memory hierarchies E Hagersten, A Sembrant, D Black-schaffer, S Kaxiras US Patent 10,402,344, 2019 | 11 | 2019 |
| Systems and methods for efficient cacheline handling based on predictions EE Hagersten, AK Sembrant, D Black-schaffer US Patent 11,138,121, 2021 | 10 | 2021 |
| Placement policy for memory hierarchies E Hagersten, A Sembrant, D Black-schaffer US Patent 10,019,368, 2018 | 10 | 2018 |
| Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement A Sembrant, E Hagersten, D Black-Schaffer 2016 IEEE 34th International Conference on Computer Design (ICCD), 117-124, 2016 | 10 | 2016 |
| Behind the scenes: Memory analysis of graphical workloads on tile-based GPUs G Ceballos, A Sembrant, TE Carlson, D Black-Schaffer 2018 IEEE International Symposium on Performance Analysis of Systems and …, 2018 | 8 | 2018 |
| Tracking alternative cacheline placement locations in a cache hierarchy E Hagersten, A Sembrant, D Black-schaffer US Patent 10,031,849, 2018 | 5 | 2018 |
David Black-SchafferProfessor, Uppsala UniversityVerified email at it.uu.se
