Junkai Jiang
Junkai Jiang
Google, UCSB ECE, PKU EECS
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Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects
J Jiang, J Kang, W Cao, X Xie, H Zhang, JH Chu, W Liu, K Banerjee
Nano letters 17 (3), 1482-1488, 2017
772017
2-D layered materials for next-generation electronics: Opportunities and challenges
W Cao, J Jiang, X Xie, A Pal, JH Chu, J Kang, K Banerjee
IEEE Transactions on Electron Devices 65 (10), 4109-4121, 2018
402018
On-chip intercalated-graphene inductors for next-generation radio frequency electronics
J Kang, Y Matsumoto, X Li, J Jiang, X Xie, K Kawamoto, M Kenmoku, ...
Nature Electronics 1 (1), 46-51, 2018
392018
Designing band-to-band tunneling field-effect transistors with 2D semiconductors for next-generation low-power VLSI
W Cao, J Jiang, J Kang, D Sarkar, W Liu, K Banerjee
2015 IEEE International Electron Devices Meeting (IEDM), 12.3. 1-12.3. 4, 2015
232015
Characterization of self-heating and current-carrying capacity of intercalation doped graphene-nanoribbon interconnects
J Jiang, J Kang, K Banerjee
2017 IEEE International Reliability Physics Symposium (IRPS), 6B-1.1-6B-1.6, 2017
202017
Ultimate monolithic-3D integration with 2D materials: rationale, prospects, and challenges
J Jiang, K Parto, W Cao, K Banerjee
IEEE Journal of the Electron Devices Society 7, 878-887, 2019
152019
All-carbon interconnect scheme integrating graphene-wires and carbon-nanotube-vias
J Jiang, J Kang, JH Chu, K Banerjee
2017 IEEE International Electron Devices Meeting (IEDM), 14.3. 1-14.3. 4, 2017
132017
CMOS-compatible doped-multilayer-graphene interconnects for next-generation VLSI
J Jiang, JH Chu, K Banerjee
2018 IEEE International Electron Devices Meeting (IEDM), 34.5. 1-34.5. 4, 2018
92018
Monolithic-3D integration with 2D materials: Toward ultimate vertically-scaled 3D-ICs
J Jiang, K Parto, W Cao, K Banerjee
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
92018
Reliability and performance of CMOS-compatible multi-level graphene interconnects incorporating vias
K Agashiwala, J Jiang, CH Yeh, K Parto, D Zhang, K Banerjee
2020 IEEE International Electron Devices Meeting (IEDM), 31.1. 1-31.1. 4, 2020
12020
Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias
K Agashiwala, J Jiang, K Parto, D Zhang, CH Yeh, K Banerjee
IEEE Transactions on Electron Devices 68 (4), 2083-2091, 2021
2021
Can Kinetic Inductance in Low-Dimensional Materials Enable a New Generation of RF-Electronics?
K Agashiwala, A Pal, W Cao, J Jiang, K Banerjee
2018 IEEE International Electron Devices Meeting (IEDM), 24.4. 1-24.4. 4, 2018
2018
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