Paolo Valente
Paolo Valente
Assistant Professor of Computer Science, UniversitÓ di Modena e Reggio Emilia - Italy
Verified email at - Homepage
Cited by
Cited by
Deterministic memory hierarchy and virtualization for modern multi-core embedded systems
T Kloda, M Solieri, R Mancuso, N Capodieci, P Valente, M Bertogna
2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTASá…, 2019
High throughput disk scheduling with fair bandwidth distribution
P Valente, F Checconi
Computers, IEEE Transactions on 59 (9), 1172-1186, 2010
SiGAMMA: Server based integrated GPU arbitration mechanism for memory accesses
N Capodieci, R Cavicchioli, P Valente, M Bertogna
Proceedings of the 25th International Conference on Real-Time Networks andá…, 2017
QFQ: Efficient packet scheduling with tight guarantees
F Checconi, L Rizzo, P Valente
IEEE/ACM Transactions on Networking 21 (3), 802-816, 2012
An upper bound to the lateness of soft real-time tasks scheduled by EDF on multiprocessors
P Valente, G Lipari
Real-Time Systems Symposium, 2005. RTSS 2005. 26th IEEE International, 10 ppá…, 2005
Exact GPS simulation with logarithmic complexity, and its application to an optimally fair scheduler
P Valente
Proceedings of the 2004 conference on Applications, technologiesá…, 2004
A memory-centric approach to enable timing-predictability within embedded many-core accelerators
P Burgio, A Marongiu, P Valente, M Bertogna
2015 CSI Symposium on Real-Time and Embedded Systems and Technologies (RTESTá…, 2015
Improving application responsiveness with the bfq disk i/o scheduler
P Valente, M Andreolini
Proceedings of the 5th Annual International Systems and Storage Conference, 1-12, 2012
A low-latency and high-throughput scheduler for emergency and wireless networks
M Casoni, CA Grazia, P Valente
2014 IEEE International Conference on Communications Workshops (ICC), 231-236, 2014
Exact gps simulation and optimal fair scheduling with logarithmic complexity
P Valente
IEEE/ACM Transactions on Networking 15 (6), 1454-1466, 2007
PSPAT: Software packet scheduling at hardware speed
L Rizzo, P Valente, G Lettieri, V Maffione
Computer Communications 120, 32-45, 2018
Integrating Linux and the real-time ERIKA OS through the Xen hypervisor
A Avanzini, P Valente, D Faggioli, P Gai
10th IEEE International Symposium on Industrial Embedded Systems (SIES), 1-7, 2015
Managing human-driven and autonomous vehicles at smart intersections
G Cabri, M Montangero, F Muzzini, P Valente
2020 IEEE International Conference on Human-Machine Systems (ICHMS), 1-4, 2020
An STDMA-based framework for QoS provisioning in wireless mesh networks
M Leoncini, P Santi, P Valente
2008 5th IEEE International Conference on Mobile Ad Hoc and Sensor Systemsá…, 2008
A survey on shared disk I/O management in virtualized environments under real time constraints
I Sa˝udo, R Cavicchioli, N Capodieci, P Valente, M Bertogna
ACM SIGBED Review 15 (1), 57-63, 2018
Reducing the execution time of fair-queueing packet schedulers
P Valente
Computer Communications 47, 16-33, 2014
An efficient algorithm for planted structured motif extraction
M Federico, P Valente, M Leoncini, M Montangero, R Cavicchioli
Proceedings of the 1st ACM workshop on Breaking frontiers of computationalá…, 2009
A parallel branch-and-bound algorithm to compute a tighter tardiness bound for preemptive global EDF
M Leoncini, M Montangero, P Valente
Real-Time Systems 55 (2), 349-386, 2019
Evolution of the BFQ Storage-I/O scheduler
P Valente, A Avanzini
2015 Mobile Systems Technologies Workshop (MST), 15-20, 2015
Using a lag-balance property to tighten tardiness bounds for global EDF
P Valente
Real-Time Systems 52, 486-561, 2016
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