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Gracieli Posser
Gracieli Posser
Senior Principal Software Engineer, Cadence Design Systems, Inc.
Verified email at inf.ufrgs.br
Title
Cited by
Cited by
Year
ISPD 2018 initial detailed routing contest and benchmarks
S Mantik, G Posser, WK Chow, Y Ding, WH Liu
Proceedings of the 2018 International Symposium on Physical Design, 140-143, 2018
632018
Effective Method for Simultaneous Gate Sizing and th Assignment Using Lagrangian Relaxation
G Flach, T Reimann, G Posser, M Johann, R Reis
IEEE transactions on computer-aided design of integrated circuits and …, 2014
602014
ISPD 2019 initial detailed routing contest and benchmark with advanced routing rules
WH Liu, S Mantik, WK Chow, Y Ding, A Farshidi, G Posser
Proceedings of the 2019 International Symposium on Physical Design, 147-151, 2019
392019
A systematic approach for analyzing and optimizing cell-internal signal electromigration
G Posser, V Mishra, P Jain, R Reis, SS Sapatnekar
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 486-491, 2014
242014
Simultaneous gate sizing and vt assignment using fanin/fanout ratio and simulated annealing
T Reimann, G Posser, G Flach, M Johann, R Reis
2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2549-2552, 2013
242013
FinFET cells with different transistor sizing techniques against PVT variations
AL Zimpeck, C Meinhardt, G Posser, R Reis
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 45-48, 2016
222016
Cell-internal electromigration: Analysis and pin placement based optimization
G Posser, V Mishra, P Jain, R Reis, SS Sapatnekar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
192015
Analyzing the electromigration effects on different metal layers and different wire lengths
G Posser, V Mishra, R Reis, SS Sapatnekar
2014 21st IEEE International Conference on Electronics, Circuits and Systems …, 2014
192014
Gate sizing minimizing delay and area
G Posser, G Flach, G Wilke, R Reis
2011 IEEE Computer Society Annual Symposium on VLSI, 315-316, 2011
152011
Cell-level signal electromigration
SS Sapatnekar, V Mishra, P Jain, G Posser, R Reis
US Patent 9,665,680, 2017
142017
Electromigration aware circuits by using special signal non-default routing rules
L de Paris, G Posser, R Reis
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2795-2798, 2016
102016
Simultaneous gate sizing and Vthassignment using Lagrangian Relaxation and delay sensitivities
G Flach, T Reimann, G Posser, M Johann, R Reis
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 84-89, 2013
102013
Gate sizing using geometric programming
G Posser, G Flach, G Wilke, R Reis
Analog Integrated Circuits and Signal Processing 73, 831-840, 2012
102012
Variabilidade em FinFETs
C Meinhardt
82014
Reducing the number of transistors with gate clustering
C Conceição, G Posser, R Reis
2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 163-166, 2016
72016
Process variability in FinFET standard cells with different transistor sizing techniques
AL Zimpeck, C Meinhardt, G Posser, R Reis
2015 IEEE International Conference on Electronics, Circuits, and Systems …, 2015
72015
Perfomance improvement with dedicated transistor sizing for mosfet and finfet devices
G Posser, J Belomo, C Meinhardt, R Reis
2014 IEEE Computer Society Annual Symposium on VLSI, 418-423, 2014
72014
A study on layout quality of automatic generated cells
G Posser, A Ziesemer, D Guimares, G Wilke, R Reis
2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010
72010
Electromigration Inside Logic Cells
G Posser, SS Sapatnekar, R Reis
Springer, 2017
62017
Reducing the signal electromigration effects on different logic gates by cell layout optimization
G Posser, L De Paris, V Mishra, P Jain, R Reis, SS Sapatnekar
2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2015
62015
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