| Investigation of multi-bit upsets in a 150 nm technology SRAM device D Radaelli, H Puchner, S Wong, S Daniel IEEE Transactions on Nuclear Science 52 (6), 2433-2437, 2005 | 287 | 2005 |
| Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for … S Aronowitz, H Puchner, RA Kapre, JP Kimball US Patent 6,331,468, 2001 | 262 | 2001 |
| SER--history, Trends and Challenges: A Guide for Designing with Memory ICs JF Ziegler, H Puchner Cypress, 2004 | 211 | 2004 |
| Silicon carbide CMOS channel H Puchner US Patent 6,358,806, 2002 | 189 | 2002 |
| The contribution of low-energy protons to the total on-orbit SEU rate NA Dodds, MJ Martinez, PE Dodd, MR Shaneyfelt, FW Sexton, JD Black, ... IEEE Transactions on Nuclear Science 62 (6), 2440-2451, 2015 | 90 | 2015 |
| Multiple cell upset classification in commercial SRAMs G Tsiligiannis, L Dilillo, A Bosio, P Girard, S Pravossoudovitch, A Todri, ... IEEE Transactions on Nuclear Science 61 (4), 1747-1754, 2014 | 71 | 2014 |
| Silicon germanium CMOS channel H Puchner, GK Giust US Patent 6,544,854, 2003 | 66 | 2003 |
| Dual nitrogen implantation techniques for oxynitride formation in semiconductor devices SF Huang, H Puchner US Patent 6,323,106, 2001 | 59 | 2001 |
| Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same H Puchner, SF Huang, S Aronowitz US Patent 6,156,620, 2000 | 57 | 2000 |
| Elimination of single event latchup in 90nm SRAM technologies H Puchner, R Kapre, S Sharifzadeh, J Majjiga, R Chao, D Radaelli, ... 2006 IEEE International Reliability Physics Symposium Proceedings, 721-722, 2006 | 50 | 2006 |
| Alpha-particle SEU performance of SRAM with triple well H Puchner, D Radaelli, A Chatila IEEE transactions on nuclear science 51 (6), 3525-3528, 2004 | 46 | 2004 |
| Process impact on SRAM alpha-particle SEU performance YZ Xu, H Puchner, A Chatila, O Pohland, B Bruggeman, B Jin, D Radaelli, ... 2004 IEEE International Reliability Physics Symposium. Proceedings, 294-299, 2004 | 44 | 2004 |
| SONOS type stacks for nonvolatile change trap memory devices and methods to form the same H Puchner, I Polishchuk, S Levy US Patent 8,163,660, 2012 | 43 | 2012 |
| NBTI reliability analysis for a 90 nm CMOS technology H Puchner, L Hinh Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat …, 2004 | 43 | 2004 |
| Process for forming thin gate oxide with enhanced reliability by nitridation of upper surface of gate of oxide to form barrier of nitrogen atoms in upper surface region of gate … S Aronowitz, J Haywood, JP Kimball, H Puchner, RM Kapre, N Eib US Patent 6,413,881, 2002 | 43 | 2002 |
| Neutron induced micro SEL events in COTS SRAM devices J Tausch, D Sleeter, D Radaelli, H Puchner 2007 IEEE Radiation Effects Data Workshop, 185-188, 2007 | 41 | 2007 |
| SRAM variability and supply voltage scaling challenges R Kapre, K Shakeri, H Puchner, J Tandigan, T Nigam, K Jang, ... 2007 IEEE International Reliability Physics Symposium Proceedings. 45th …, 2007 | 40 | 2007 |
| Dynamic test methods for COTS SRAMs G Tsiligiannis, L Dilillo, V Gupta, A Bosio, P Girard, A Virazel, H Puchner, ... IEEE Transactions on Nuclear Science 61 (6), 3095-3102, 2014 | 39 | 2014 |
| SER-history JF Ziegler, H Puchner Trends, and Challenges: A Guide for Designing with Memory ICs, 2004 | 38 | 2004 |
| High-voltage CMOS ESD and the safe operating area AJ Walker, H Puchner, SP Dhanraj IEEE Transactions on Electron Devices 56 (8), 1753-1760, 2009 | 37 | 2009 |
