The gem5 simulator N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ... ACM SIGARCH computer architecture news 39 (2), 1-7, 2011 | 6193 | 2011 |
Decoupled compressed cache: Exploiting spatial locality for energy-optimized compressed caching S Sardashti, DA Wood Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 121 | 2013 |
Skewed compressed caches S Sardashti, A Seznec, DA Wood 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 331-342, 2014 | 86 | 2014 |
The Gem5 Simulator. SIGARCH Comput. Archit. News 39, 2 (Aug. 2011), 1–7 N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ... | 81 | 2011 |
Yet another compressed cache: A low-cost yet effective compressed cache S Sardashti, A Seznec, DA Wood ACM Transactions on Architecture and Code Optimization (TACO) 13 (3), 1-25, 2016 | 56 | 2016 |
A primer on compression in the memory hierarchy S Sardashti, A Arelakis, P Stenström, DA Wood Morgan & Claypool, 2016 | 35 | 2016 |
F1 query: Declarative querying at scale B Samwel, J Cieslewicz, B Handy, J Govig, P Venetis, C Yang, K Peters, ... Proceedings of the VLDB Endowment 11 (12), 1835-1848, 2018 | 32 | 2018 |
Thread-sensitive instruction issue for smt processors B Robatmili, N Yazdani, S Sardashti, M Nourani IEEE Computer Architecture Letters 3 (1), 5-5, 2004 | 23 | 2004 |
Could compression be of general use? evaluating memory compression across domains S Sardashti, DA Wood ACM Transactions on Architecture and Code Optimization (TACO) 14 (4), 1-24, 2017 | 22 | 2017 |
Decoupled compressed cache: Exploiting spatial locality for energy optimization S Sardashti, DA Wood IEEE Micro 34 (3), 91-99, 2014 | 20 | 2014 |
UniFI: leveraging non-volatile memories for a unified fault tolerance and idle power management technique S Sardashti, DA Wood Proceedings of the 26th ACM international conference on Supercomputing, 59-68, 2012 | 11 | 2012 |
Using compression for energy-optimized memory hierarchies S Sardashti The University of Wisconsin-Madison, 2015 | 2 | 2015 |
Multi-Issue Multi-Threaded Stream Processor S Sardashti, HR Ghasemi, O Fatemi Multimedia and Expo, 2006 IEEE International Conference on, 2041-2044, 2006 | 1 | 2006 |
Cache Compression S Sardashti, A Arelakis, P Stenström, DA Wood A Primer on Compression in the Memory Hierarchy, 21-32, 2016 | | 2016 |
Compression Algorithms S Sardashti, A Arelakis, P Stenström, DA Wood A Primer on Compression in the Memory Hierarchy, 3-19, 2016 | | 2016 |
Cache/Memory Link Compression S Sardashti, A Arelakis, P Stenström, DA Wood A Primer on Compression in the Memory Hierarchy, 45-51, 2016 | | 2016 |
Memory Compression S Sardashti, A Arelakis, P Stenström, DA Wood A Primer on Compression in the Memory Hierarchy, 33-43, 2016 | | 2016 |
Energy optimized cache memory architecture exploiting spatial locality S Sardashti, D Wood US Patent US 2014/0108731 A1, 2014 | | 2014 |
High Performance Mathematical Quarter-Pixel Motion Estimation with Novel Rate Distortion Metric for H. 264/AVC S Sardashti, HR Ghasemi, M Semsarzadeh, MR Hashemi Advances in Computer Science and Engineering: 13th International CSI …, 2009 | | 2009 |
MVSP: multithreaded VLIW stream processor S Sardashti, HR Ghasemi, O Fatemi Multimedia on Mobile Devices II 6074, 113-121, 2006 | | 2006 |