Malware-aware processors: A framework for efficient online malware detection M Ozsoy, C Donovick, I Gorelik, N Abu-Ghazaleh, D Ponomarev 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 204 | 2015 |
Branch regulation: Low-overhead protection from code reuse attacks M Kayaalp, M Ozsoy, N Abu-Ghazaleh, D Ponomarev ACM SIGARCH Computer Architecture News 40 (3), 94-105, 2012 | 133 | 2012 |
Iso-x: A flexible architecture for hardware-managed isolated execution D Evtyushkin, J Elwell, M Ozsoy, D Ponomarev, NA Ghazaleh, R Riley 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 190-202, 2014 | 128 | 2014 |
Ensemble learning for low-level hardware-supported malware detection KN Khasawneh, M Ozsoy, C Donovick, N Abu-Ghazaleh, D Ponomarev International Symposium on Recent Advances in Intrusion Detection, 3-25, 2015 | 125 | 2015 |
Hardware-based malware detection using low-level architectural features M Ozsoy, KN Khasawneh, C Donovick, I Gorelik, N Abu-Ghazaleh, ... IEEE Transactions on Computers 65 (11), 3332-3344, 2016 | 105 | 2016 |
EnsembleHMD: Accurate hardware malware detectors with specialized ensemble classifiers KN Khasawneh, M Ozsoy, C Donovick, N Abu-Ghazaleh, D Ponomarev IEEE Transactions on Dependable and Secure Computing 17 (3), 620-633, 2018 | 52 | 2018 |
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors M Ozsoy, D Ponomarev, N Abu-Ghazaleh, T Suri Proceedings of the 8th ACM International Conference on Computing Frontiers, 37, 2011 | 44 | 2011 |
Unblock instruction to reverse page block during paging CV Rozas, I Anati, FX McKeen, K Zmudzinski, I Alexandrovich, ... US Patent 10,552,344, 2020 | 41 | 2020 |
Efficiently securing systems from code reuse attacks M Kayaalp, M Ozsoy, NA Ghazaleh, D Ponomarev IEEE Transactions on Computers 63 (5), 1144-1156, 2012 | 41 | 2012 |
Flexible hardware-managed isolated execution: Architecture, software support and applications D Evtyushkin, J Elwell, M Ozsoy, D Ponomarev, NA Ghazaleh, R Riley IEEE Transactions on Dependable and Secure Computing 15 (3), 437-451, 2016 | 17 | 2016 |
Application execution enclave memory method and apparatus V Shanbhogue, I Anati, FX McKeen, KC Zmudzinski, M Ozsoy US Patent 10,671,542, 2020 | 12 | 2020 |
SIFT: low-complexity energy-efficient information flow tracking on SMT processors M Ozsoy, D Ponomarev, N Abu-Ghazaleh, T Suri IEEE Transactions on Computers 63 (2), 484-496, 2012 | 10 | 2012 |
Host-convertible secure enclaves in memory that leverage multi-key total memory encryption with integrity KC Zmudzinski, SP Johnson, R Makaram, FX McKeen, CV Rozas, ... US Patent 11,030,120, 2021 | 9 | 2021 |
Hardware support for static mode of protected memory management on flexibly-convertible enclave platform M Ozsoy, V Shanbhogue, KC Zmudzinski, FX McKeen, CV Rozas, ... US Patent App. 15/719,222, 2019 | 8 | 2019 |
Tracking and managing translation lookaside buffers KC Zmudzinski, CV Rozas, FX McKeen, RM Leslie-Hurd, M Ozsoy, ... US Patent 10,540,291, 2020 | 7 | 2020 |
Cache behavior for secure memory repartitioning systems M Ozsoy, KC Zmudzinski, L Novakovsky, J Mandelblat, FX McKeen, ... US Patent App. 15/721,631, 2019 | 7 | 2019 |
Dynamic associative caches: Reducing dynamic energy of first level caches K Dayalan, M Ozsoy, D Ponomarev 2014 IEEE 32nd International Conference on Computer Design (ICCD), 118-124, 2014 | 7 | 2014 |
Processor instruction support to defeat side-channel attacks F Liu, B Xing, M Steiner, M Vij, C Rozas, F McKeen, M Ozsoy, ... US Patent 10,922,088, 2021 | 4 | 2021 |
Processor instruction support for mitigating controlled-channel and cache-based side-channel attacks S Constable, F Liu, B Xing, M Steiner, M Vij, C Rozas, FX McKeen, ... US Patent App. 16/458,015, 2020 | 4 | 2020 |
Secure memory repartitioning technologies V Shanbhogue, KC Zmudzinski, CV Rozas, FX McKeen, R Makaram, ... US Patent 10,628,315, 2020 | 4 | 2020 |