| Decimal multiplication using compact BCD multiplier RK James, TK Shahana, KP Jacob, S Sasi 2008 International Conference on Electronic Design, 1-6, 2008 | 42 | 2008 |
| Polyphase implementation of non-recursive comb decimators for sigma-delta A/D converters TK Shahana, RK James, BR Jose, KP Jacob, S Sasi 2007 IEEE Conference on Electron Devices and Solid-State Circuits, 825-828, 2007 | 39 | 2007 |
| Fault tolerant error coding and detection using reversible gates RK James, KP Jacob, S Sasi TENCON 2007-2007 IEEE Region 10 Conference, 1-4, 2007 | 32 | 2007 |
| Performance analysis of FIR digital filter design: RNS versus traditional TK Shahana, RK James, BR Jose, KP Jacob, S Sasi 2007 International Symposium on Communications and Information Technologies, 1-5, 2007 | 31 | 2007 |
| High throughput FIR filter architectures using retiming and modified CSLA based adders P Patali, S Thottathikkulam Kassim IET Circuits, Devices & Systems 13 (7), 1007-1017, 2019 | 30 | 2019 |
| Efficient modular hybrid adders and Radix-4 booth multipliers for DSP applications P Patali, ST Kassim Microelectronics Journal 96, 104701, 2020 | 27 | 2020 |
| A new look at reversible logic implementation of decimal adder RK James, TK Shahana, KP Jacob, S Sasi 2007 International Symposium on System-on-Chip, 1-4, 2007 | 20 | 2007 |
| Decimation Filter Design Toolbox for Multi-Standard Wireless Transceivers using MATLAB. K Poulose Jacob, S Sasi, JR Babita, TK Shahana International Journal of Signal Processing, 2009 | 16 | 2009 |
| An efficient architecture for signed carry save multiplication P Patali, ST Kassim IEEE Letters of the Computer Society 3 (1), 9-12, 2020 | 13 | 2020 |
| New results in related key impossible differential cryptanalysis on reduced round AES-192 KB Jithendra, TK Shahana 2018 International Conference On Advances in Communication and Computing …, 2018 | 12 | 2018 |
| Delay and energy efficient modular hybrid adder for signal processor architectures P Pramod, TK Shahana IETE Journal of Research 68 (2), 924-934, 2022 | 11 | 2022 |
| RRNS-convolutional concatenated code for OFDM based wireless communication with direct analog-to-residue converter TK Shahana, BR Jose, KP Jacob, S Sasi International Journal of Electronics and Communication Engineering 2 (9 …, 2008 | 10 | 2008 |
| High throughput adaptive filter architecture using modified transpose form FIR filters P Pramod, TK Shahana J. Adv. Res. Dyn. Control Syst 10 (15), 68-82, 2018 | 9 | 2018 |
| RNS based programmable multi-mode decimation filter for WCDMA and WiMAX TK Shahana, BR Jose, RK James, KP Jacob, S Sasi VTC Spring 2008-IEEE Vehicular Technology Conference, 1831-1835, 2008 | 9 | 2008 |
| Improved reversible logic implementation of decimal adder R James, TK Shahana, KP Jacob, S Sasi IEEE 11th VDAT Symposium Aug 8 (11), 2007 | 9 | 2007 |
| Design of 1-Bit DAC for Delta-Sigma Modulator RP Thankachan, R JayakrishnanK, K ShahanaT Int. J. Comput. Appl., 975-8887, 2015 | 8 | 2015 |
| Design and synthesis of FIR filter banks using area and power efficient Stochastic Computing VV Mahesh, TK Shahana 2020 Fourth World Conference on Smart Trends in Systems, Security and …, 2020 | 7 | 2020 |
| Isolated switched boost DC-DC converter with coupled inductor and transformer P Paul, BR Jose, TK Shahana, C Abraham, J Mathew TENCON 2019-2019 IEEE Region 10 Conference (TENCON), 1142-1147, 2019 | 7 | 2019 |
| Dual-mode RNS based programmable decimation filter for WCDMA and WLANa TK Shahana, BR Jose, RK James, KP Jacob, S Sasi 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 952-955, 2008 | 7 | 2008 |
| Constrained least square nonuniform dynamic filter bank for delay and Hardware efficient digital hearing aids VV Mahesh, TK Shahana Health and Technology 9, 355-363, 2019 | 6 | 2019 |
Dr. Poulose Jacob K.Professor of Computer Science & Pro VC - Emeritus, COCHIN University of Science & TechnologyVerified email at cusat.ac.in
