| A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC) JN Soares, WAM Van Noije IEEE journal of solid-state circuits 34 (1), 97-102, 1999 | 188 | 1999 |
| Precise final state determination of mismatched CMOS latches WAM Van Noije, WT Liu, SJ Navarro IEEE journal of solid-state circuits 30 (5), 607-611, 1995 | 33 | 1995 |
| Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design SJ Navarro, WAM Van Noije IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10 (3), 301-308, 2002 | 32 | 2002 |
| A methodology for CMOS low noise amplifier design E Roa, JN Soares, W Van Noije 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003 …, 2003 | 25 | 2003 |
| A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35 ͘m CMOS technology FPH de Miranda, J Navarro S Jr, WAM Van Noije Proceedings of the 17th symposium on Integrated circuits and system design …, 2004 | 24 | 2004 |
| A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer AM Gómez Argüello, J Navarro, W Van Noije Proceedings of the 18th annual symposium on Integrated circuits and system …, 2005 | 17 | 2005 |
| A CMOS implementation of the sine-circle map A Farfan-Pelaez, E Del-Moral-Hernández, JS Navarro, W Van Noije 48th Midwest Symposium on Circuits and Systems, 2005., 1502-1505, 2005 | 16 | 2005 |
| E-TSPC: Extended True Single-Phase-Clock CMOS circuit technique J Navarro S Jr, WAM Van Noije VLSI: Integrated Systems on Silicon: IFIP TC10 WG10. 5 International …, 1997 | 13 | 1997 |
| Metastability behavior of mismatched CMOS flip-flops using state diagram analysis WAM Van Noije, WT Liu, J Navarro Proceedings of IEEE Custom Integrated Circuits Conference-CICC'93, 27.7. 1 …, 1993 | 13 | 1993 |
| A simple CMOS bandgap reference circuit with sub-1-V operation J Navarro, E Ishibe 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2289-2292, 2011 | 12 | 2011 |
| E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications JN Soares Junior, WAM Van Noije Journal of Solid-State Devices and Circuits 5 (2), 21-26, 1997 | 10 | 1997 |
| Design of an OTA-Miller for a 96dB SNR SC multi-bit Sigma-Delta modulator based on gm/ID methodology HA Cubas, J Navarro 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), 1-4, 2013 | 9 | 2013 |
| A small area 8bits 50MHz CMOS DAC for bluetooth transmitter HD Hernández, W Van Noije, E Roa, J Navarro Proceedings of the 20th annual conference on Integrated circuits and systems …, 2007 | 8 | 2007 |
| Técnicas para projetos de ASICs CMOS de alta velocidade J Navarro Doctoral’s thesis, University of São Paulo, Polytechnic School of São Paulo …, 1998 | 8 | 1998 |
| A power optimized decimator for sigma-delta data converters D de Carvalho, J Navarro 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), 1-4, 2013 | 7 | 2013 |
| Design of an 8: 1 MUX at 1.7 Gbit/s in 0.8/spl mu/m CMOS technology J Navarro, WAM Van Noije Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No. 98TB100222 …, 1998 | 7 | 1998 |
| 1.2 Gb/s SONET/SDH demux in CMOS technology FL Romão, JN Soares, R Silveira, WAM Van Noije Proceedings of 1995 SBMO/IEEE MTT-S International Microwave and …, 1995 | 6 | 1995 |
| Design of high speed digital circuits with E-TSPC cell library J Navarro, G Martins Proceedings of the 24th symposium on Integrated circuits and systems design …, 2011 | 5 | 2011 |
| Circuitos integrados cmos ST Kofuji, JA Zuffo, JN Soares Disciplina de Eletrônica Experimental, 1990 | 4 | 1990 |
| Charge-pump circuit in 65nm CMOS for neural stimulation on deep-brain stimulation TM Nordi, VM Barbosa, RH Gounella, G Asan, M Luppe, J Navarro, ... 2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS), 1-4, 2021 | 3 | 2021 |
