Samuel Pagliarini
Samuel Pagliarini
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Analyzing the impact of single-event-induced charge sharing in complex circuits
S Pagliarini, F Kastensmidt, L Entrena, A Lindoso, E San Millan
IEEE Transactions on Nuclear Science 58 (6), 2768-2775, 2011
A flexible online checking technique to enhance hardware trojan horse detectability by reliability analysis
RS Chakraborty, S Pagliarini, J Mathew, SR Rajendran, MN Devi
IEEE Transactions on Emerging Topics in Computing 5 (2), 260-270, 2017
Selective hardening methodology for combinational logic
SN Pagliarini, LAB Naviner, JF Naviner
2012 13th latin American test workshop (LATW), 1-6, 2012
Constrained placement methodology for reducing SER under single-event-induced charge sharing effects
L Entrena, A Lindoso, E San Millan, S Pagliarini, F Almeida, ...
IEEE Transactions on Nuclear Science 59 (4), 811-817, 2012
A fault tolerant approach to detect transient faults in microprocessors based on a non-intrusive reconfigurable hardware
JR Azambuja, S Pagliarini, M Altieri, FL Kastensmidt, M Hubner, J Becker, ...
IEEE Transactions on Nuclear Science 59 (4), 1117-1124, 2012
Exploring the feasibility of selective hardening for combinational logic
SN Pagliarini, GG dos Santos, LAB Naviner, JF Naviner
Microelectronics Reliability 52 (9-10), 1843-1847, 2012
Exploring the limitations of software-based techniques in SEE fault coverage
JR Azambuja, S Pagliarini, L Rosa, FL Kastensmidt
Journal of Electronic Testing 27 (4), 541-550, 2011
A placement strategy for reducing the effects of multiple faults in digital circuits
SN Pagliarini, D Pradhan
2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 69-74, 2014
Snap: A novel hybrid method for circuit reliability assessment under multiple faults
SN Pagliarini, AB Dhia, LAB Naviner, JF Naviner
Microelectronics Reliability 53 (9-11), 1230-1234, 2013
A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs
AB Dhia, SN Pagliarini, LAB Naviner, H Mehrez, P Matherat
Microelectronics Reliability 53 (9-11), 1189-1193, 2013
Selective hardening methodology concerning multiple faults
SN Pagliarini, LA de Barros Naviner, JF Naviner
IEEE Nuclear and Space Radiation Effects Conference, 2012
An oscillatory neural network with programmable resistive synapses in 28 nm CMOS
T Jackson, S Pagliarini, L Pileggi
2018 IEEE International Conference on Rebooting Computing (ICRC), 1-7, 2018
Virtual characterization for exhaustive DFM evaluation of logic cell libraries
S Pagliarini, M Martins, L Pileggi
2017 18th International Symposium on Quality Electronic Design (ISQED), 93-98, 2017
Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits
MI Bandan, S Pagliarini, J Mathew, D Pradhan
IEEE Transactions on Reliability 66 (1), 233-244, 2017
Latch-based logic locking
J Sweeney, VM Zackriya, S Pagliarini, L Pileggi
2020 IEEE International Symposium on Hardware Oriented Security and Trust …, 2020
Application and product-volume-specific customization of BEOL metal pitch
SN Pagliarini, MM Isgenc, MGA Martins, L Pileggi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (9 …, 2018
A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ
S Bhuin, J Sweeney, S Pagliarini, AK Biswas, L Pileggi
2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2017
Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis
SN Pagliarini, T Ban, LAB Naviner, JF Naviner
2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013
A survey on split manufacturing: Attacks, defenses, and challenges
TD Perez, S Pagliarini
IEEE Access 8, 184013-184035, 2020
Split-Chip Design to prevent IP Reverse Engineering
S Pagliarini, J Sweeney, K Mai, S Blanton, S Mitra, L Pileggi
IEEE Design and Test, 2020
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