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Jarbas Silveira
Jarbas Silveira
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A security aware routing approach for NoC-based MPSoCs
R Fernandes, C Marcon, R Cataldo, J Silveira, G Sigl, J Sepúlveda
2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2016
412016
A correction code for multiple cells upsets in memory devices for space applications
HS Castro, JAN da Silveira, AAP Coelho, FGA e Silva, PS Magalhães, ...
2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2016
332016
Preprocessing of Scenarios for Fast and Efficient Routing Reconfiguration in Fault-Tolerant NoCs
J Silveira, C Marcon, P Cortez, G Barroso, JM Ferreira, R Mota
2015 23rd Euromicro International Conference on Parallel, Distributed, and …, 2015
302015
Performance analysis of depth intra-coding in 3D-HEVC
G Sanchez, J Silveira, LV Agostini, C Marcon
IEEE Transactions on Circuits and Systems for Video Technology 29 (8), 2509-2520, 2018
192018
An extensible code for correcting multiple cell upset in memory arrays
F Silva, J Silveira, J Silveira, C Marcon, F Vargas, O Lima
Journal of Electronic Testing 34, 417-433, 2018
162018
An efficient, low-cost ECC approach for critical-application memories
F Silva, O Lima, W Freitas, F Vargas, J Silveira, C Marcon
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design …, 2017
112017
Scenario preprocessing approach for the reconfiguration of fault-tolerant NoC-based MPSoCs
J Silveira, C Marcon, P Cortez, G Barroso, JM Ferreira, R Mota
Microprocessors and Microsystems 40, 137-153, 2016
112016
Extended matrix region selection code: An ECC for adjacent multiple cell upset in memory arrays
F Silva, W Freitas, J Silveira, C Marcon, F Vargas
Microelectronics Reliability 106, 113582, 2020
102020
CLC-A: An adaptive implementation of the Column Line Code (CLC) ECC
F Silva, A Muniz, J Silveira, C Marcon
2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2020
92020
Evaluation of multiple bit upset tolerant codes for NoCs buffering
F Silva, W Magalhães, J Silveira, JM Ferreira, P Magalhães, OA Lima, ...
2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2017
92017
Optimized fault-tolerant buffer design for network-on-chip applications
AC Pinheiro, JAN Silveira, DAB Tavares, FGA Silva, CAM Marcon
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), 217-220, 2019
72019
Efficient routing table minimization for fault-tolerant irregular network-on-chip
RG Mota, J Silveira, J Silveira, L Brahm, A Zorzo, F Mór, C Marcon
2016 IEEE International Conference on Electronics, Circuits and Systems …, 2016
72016
LPC: An error correction code for mitigating faults in 3D memories
DCC Freitas, DFM Mota, C Marcon, JAN Silveira, JCM Mota
IEEE Transactions on Computers 70 (11), 2001-2012, 2020
62020
PCoSA: A product error correction code for use in memory devices targeting space applications
D Freitas, D Mota, R Goerl, C Marcon, F Vargas, J Silveira, J Mota
Integration 74, 71-80, 2020
62020
Analysis of routing algorithms generation for irregular noc topologies
R Milfont, P Cortez, A Pinheiro, J Ferreira, J Silveira, R Mota, C Marcon
2017 18th IEEE Latin American Test Symposium (LATS), 1-5, 2017
52017
Efficient traffic balancing for NoC routing latency minimization
JM Ferreira, J Silveira, J Silveira, R Cataldo, T Webber, FG Moraes, ...
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2599-2602, 2016
52016
A Triple Burst Error Correction Based on Region Selection Code
F Silva, AC Pinheiro, JAN Silveira, C Marcon
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (8 …, 2023
42023
Optimized buffer protection for network-on-chip based on Error Correction Code
A Pinheiro, D Tavares, F Silva, J Silveira, C Marcon
Microelectronics Journal 100, 104799, 2020
42020
A fault prediction module for a fault tolerant NoC operation
J Silveira, M Bodin, JM Ferreira, AC Pinheiro, T Webber, C Marcon
Sixteenth International Symposium on Quality Electronic Design, 284-288, 2015
42015
Employing a timed colored petri net to accomplish an accurate model for network-on-chip performance evaluation
J Silveira, PC Cortez, GC Barroso, C Marcon
Fifteenth International Symposium on Quality Electronic Design, 55-59, 2014
42014
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