Leonardo Rezende Juracy
Leonardo Rezende Juracy
E-mail confirmado em acad.pucrs.br
Título
Citado por
Citado por
Ano
Optimized design of an LSSD scan cell
LR Juracy, MT Moreira, FA Kuentzer, A de Morais Amory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (2), 765-768, 2016
62016
A fast runtime fault recovery approach for NoC-based MPSoCS for performance constrained applications
E Wachter, A Erichsen, L Juracy, A Amory, FG Moraes
2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-7, 2014
52014
Runtime fault recovery protocol for NoC-based MPSoCs
E Wächter, A Erichsen, L Juracy, A Amory, F Moraes
Fifteenth International Symposium on Quality Electronic Design, 132-139, 2014
52014
A DfT Insertion Methodology to Scannable Q-Flop Elements
LR Juracy, MT Moreira, FA Kuentzer, AM Amory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (8 …, 2018
32018
On the reuse of timing resilient architecture for testing path delay faults in critical paths
FA Kuentzer, LR Juracy, AM Amory
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 379-384, 2018
32018
Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template
FA Kuentzer, LR Juracy, MT Moreira, AM Amory
2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2018
22018
An LSSD Compliant Scan Cell for Flip-Flops
LR Juracy, MT Moreira, FA Kuentzer, FG Moraes, AM Amory
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
22018
Delay lines test method for the Blade Template
FA Kuentzer, LR Juracy, MT Moreira, AM Amory
arXiv preprint arXiv:1905.11218, 2019
12019
XGT4: An industrial grade, open source tester for multi-gigabit networks
LR Juracy, FB Lazzarotto, D Pigatto, NLV Calazans, FG Moraes
2017 24th IEEE International Conference on Electronics, Circuits and Systems …, 2017
12017
A Survey of Aging Monitors and Reconfiguration Techniques
LR Juracy, MT Moreira, AM Amory, FG Moraes
arXiv preprint arXiv:2007.07829, 2020
2020
Test oriented design and layout generation of an asynchronous controller for the blade template
FA Kuentzer, LR Juracy, MT Moreira, AM Amory
2020 26th IEEE International Symposium on Asynchronous Circuits and Systems …, 2020
2020
Testing the blade resilient asynchronous template
FA Kuentzer, LR Juracy, MT Moreira, AM Amory
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2020
2020
Testing the blade resilient asynchronous template: a structural approach
LR Juracy
Pontifícia Universidade Católica do Rio Grande do Sul, 2018
2018
Design Flow for Retiming: A Case Study on a Cryptographic Core
WL Neto, LR Juracy, FA Kuentzer, MT Moreira, AM Amory
O sistema não pode executar a operação agora. Tente novamente mais tarde.
Artigos 1–14