Yogesh S. Chauhan

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sourabh khandelwalUC BerkeleyE-mail confirmado em berkeley.edu
chenming huUniversity of California, BerkeleyE-mail confirmado em eecs.berkeley.edu
Amit AgarwalProfessor, Indian Institute of Technology, Kanpur (India)E-mail confirmado em iitk.ac.in
Girish PahwaAssistant Professor, ICST, National Yang Ming Chiao Tung UniversityE-mail confirmado em nycu.edu.tw
Hussam AmrouchProfessor (W3) of AI Processor Design, Technical University of MunichE-mail confirmado em tum.de
Pragya KushwahaIIT JodhpurE-mail confirmado em iitj.ac.in
Avirup DasguptaIndian Institute of Technology RoorkeeE-mail confirmado em ece.iitr.ac.in
Somnath BhowmickInian Institute of Technology, KanpurE-mail confirmado em iitk.ac.in
Ali M NIKNEJADUC BerkeleyE-mail confirmado em berkeley.edu
Sheikh Aamir AhsanNanoelectronics Research & Development Lab, NITSRIE-mail confirmado em nitsri.ac.in
Sudip GhoshDST Young Scientist, IIT-KanpurE-mail confirmado em iitk.ac.in
Sriramkumar VenugopalanSemiconductors ProfessionalE-mail confirmado em eecs.berkeley.edu
A.M. IonescuProfessor of NanoelectronicsE-mail confirmado em epfl.ch
Chandan YadavAssistant professor, Indian Institute of Technology JammuE-mail confirmado em iitjammu.ac.in
Chetan Kumar DabhiUniversity of California, BerkeleyE-mail confirmado em berkeley.edu
Priyank RastogiIntel Technologies India Pvt. Ltd.E-mail confirmado em intel.com
Navid PaydavosiDevice Engineer, IntelE-mail confirmado em intel.com
Ahtisham PamporiUniversity of California, BerkeleyE-mail confirmado em berkeley.edu
Amol GaidhaneMTS, GlobalFoundries || Post-Doc, Arizona State University || Ph.D., IIT KanpurE-mail confirmado em globalfoundries.com
Amit VermaDepartment of Electrical Engineering, Indian Institute of Technology KanpurE-mail confirmado em iitk.ac.in

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Yogesh S. Chauhan

Fellow IEEE, FNAE, Professor-IIT Kanpur

E-mail confirmado em iitk.ac.in - Página inicial

ASM GaN HEMT Compact Model BSIM SPICE Model Cryogenic Transistor Modeling Ferroelectric Negative Capacitance Transistor


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FinFET modeling for IC simulation and design: using the BSIM-CMG standard YS Chauhan, D Lu, S Vanugopalan, S Khandelwal, JP Duarte, ... Academic Press, 2015	240	2015
Analysis and compact modeling of negative capacitance transistor with high ON-current and negative output differential resistance—Part II: Model validation G Pahwa, T Dutta, A Agarwal, S Khandelwal, S Salahuddin, C Hu, ... IEEE Transactions on Electron Devices 63 (12), 4986-4992, 2016	215	2016
Analytical modeling of surface-potential and intrinsic charges in AlGaN/GaN HEMT devices S Khandelwal, YS Chauhan, TA Fjeldly IEEE Transactions on Electron Devices 59 (10), 2856-2860, 2012	180	2012
Numerical investigation of short-channel effects in negative capacitance MFIS and MFMIS transistors: Subthreshold behavior G Pahwa, A Agarwal, YS Chauhan IEEE Transactions on Electron Devices 65 (11), 5130-5136, 2018	143	2018
BSIM6: Analog and RF compact model for bulk MOSFET YS Chauhan, S Venugopalan, MA Chalkiadaki, MAU Karim, H Agarwal, ... IEEE Transactions on Electron Devices 61 (2), 234-244, 2013	140	2013
BSIM—SPICE models enable FinFET and UTB IC designs N Paydavosi, S Venugopalan, YS Chauhan, JP Duarte, S Jandhyala, ... IEEE Access 1, 201-215, 2013	140	2013
ASM GaN: Industry standard model for GaN RF and power devices—Part 1: DC, CV, and RF model S Khandelwal, YS Chauhan, TA Fjeldly, S Ghosh, A Pampori, D Mahajan, ... IEEE Transactions on Electron Devices 66 (1), 80-86, 2018	134	2018
Physical insights on negative capacitance transistors in nonhysteresis and hysteresis regimes: MFMIS versus MFIS structures G Pahwa, T Dutta, A Agarwal, YS Chauhan IEEE Transactions on Electron Devices 65 (3), 867-873, 2018	134	2018
Robust surface-potential-based compact model for GaN HEMT IC design S Khandelwal, C Yadav, S Agnihotri, YS Chauhan, A Curutchet, T Zimmer, ... IEEE Transactions on Electron Devices 60 (10), 3216-3222, 2013	131	2013
BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with back-gate control S Khandelwal, YS Chauhan, DD Lu, S Venugopalan, MAU Karim, ... IEEE Transactions on Electron Devices 59 (8), 2019-2026, 2012	120	2012
Doping Strategies for Monolayer MoS₂ via Surface Adsorption: A Systematic Study P Rastogi, S Kumar, S Bhowmick, A Agarwal, YS Chauhan The Journal of Physical Chemistry C 118 (51), 30309-30314, 2014	117	2014
Compact model for ferroelectric negative capacitance transistor with MFIS structure G Pahwa, T Dutta, A Agarwal, YS Chauhan IEEE Transactions on Electron Devices 64 (3), 1366-1374, 2017	113	2017
Analytical modeling of the suspended-gate FET and design insights for low-power logic K Akarvardar, C Eggimann, D Tsamados, YS Chauhan, GC Wan, ... IEEE transactions on Electron Devices 55 (1), 48-59, 2007	110	2007
Thickness and electric-field-dependent polarizability and dielectric constant in phosphorene P Kumar, BS Bhadoria, S Kumar, S Bhowmick, YS Chauhan, A Agarwal Physical Review B 93 (19), 195428, 2016	104	2016
Capacitance modeling in dual field-plate power GaN HEMT for accurate switching behavior SA Ahsan, S Ghosh, K Sharma, A Dasgupta, S Khandelwal, YS Chauhan IEEE Transactions on Electron Devices 63 (2), 565-572, 2015	99	2015
BSIM-CMG: Standard FinFET compact model for advanced circuit design JP Duarte, S Khandelwal, A Medury, C Hu, P Kushwaha, H Agarwal, ... ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015	97	2015
Performance evaluation of 7-nm node negative capacitance FinFET-based SRAM T Dutta, G Pahwa, AR Trivedi, S Sinha, A Agarwal, YS Chauhan IEEE Electron Device Letters 38 (8), 1161-1164, 2017	94	2017
RF SOI switch FET design and modeling tradeoffs for GSM applications S Parthasarathy, A Trivedi, S Sirohi, R Groves, M Olsen, YS Chauhan, ... 2010 23rd International Conference on VLSI Design, 194-199, 2010	91	2010
ASM GaN: Industry standard model for GaN RF and power devices—Part-II: Modeling of charge trapping SA Albahrani, D Mahajan, J Hodges, YS Chauhan, S Khandelwal IEEE Transactions on Electron Devices 66 (1), 87-94, 2018	88	2018
BSIM—Industry standard compact MOSFET models YS Chauhan, S Venugopalan, MA Karim, S Khandelwal, N Paydavosi, ... 2012 Proceedings of the European Solid-State Device Research Conference …, 2012	85	2012

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