| Capability hardware enhanced RISC instructions: CHERI instruction-set architecture (version 7) RNM Watson, PG Neumann, J Woodruff, M Roe, H Almatary, J Anderson, ... University of Cambridge, Computer Laboratory, 2019 | 128 | 2019 |
| CheriABI: Enforcing valid pointer provenance and minimizing pointer privilege in the POSIX C run-time environment B Davis, RNM Watson, A Richardson, PG Neumann, SW Moore, ... Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 92 | 2019 |
| Cornucopia: Temporal safety for CHERI heaps NW Filardo, BF Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, B Davis, ... 2020 IEEE Symposium on Security and Privacy (SP), 608-625, 2020 | 82 | 2020 |
| Efficient tagged memory A Joannou, J Woodruff, R Kovacsics, SW Moore, A Bradbury, H Xia, ... 2017 IEEE International Conference on Computer Design (ICCD), 641-648, 2017 | 78 | 2017 |
| Cheri concentrate: Practical compressed capabilities J Woodruff, A Joannou, H Xia, A Fox, RM Norton, D Chisnall, B Davis, ... IEEE Transactions on Computers 68 (10), 1455-1469, 2019 | 74 | 2019 |
| Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process K Nienhuis, A Joannou, T Bauereiss, A Fox, M Roe, B Campbell, M Naylor, ... 2020 IEEE Symposium on Security and Privacy (SP), 1003-1020, 2020 | 57 | 2020 |
| Fast protection-domain crossing in the CHERI capability-system architecture RNM Watson, RM Norton, J Woodruff, SW Moore, PG Neumann, ... IEEE Micro 36 (5), 38-49, 2016 | 57 | 2016 |
| CHERI JNI: Sinking the Java security model into the C D Chisnall, B Davis, K Gudka, D Brazdil, A Joannou, J Woodruff, ... ACM SIGARCH Computer Architecture News 45 (1), 569-583, 2017 | 50 | 2017 |
| Capability hardware enhanced RISC instructions: CHERI instruction-set architecture RNM Watson, PG Neumann, J Woodruff, M Roe, J Anderson, D Chisnall, ... University of Cambridge, Computer Laboratory, 2015 | 34 | 2015 |
| Cherirtos: A capability model for embedded devices H Xia, J Woodruff, H Barral, L Esswood, A Joannou, R Kovacsics, ... 2018 IEEE 36th International Conference on Computer Design (ICCD), 92-99, 2018 | 30 | 2018 |
| High-performance memory safety: optimizing the CHERI capability machine AJP Joannou University of Cambridge, Computer Laboratory, 2019 | 9 | 2019 |
| Modular research-based composably trustworthy mission-oriented resilient clouds (mrc2) PG Neumann, SW Moore, RN Watson, J Anderson, N Dave, B Davis, ... SRI INTERNATIONAL Menlo Park United States, Tech. Rep, 2016 | 2 | 2016 |
| Randomized testing of RISC-V CPUs using direct instruction injection A Joannou, P Rugg, J Woodruff, FA Fuchs, M Van der Maas, M Naylor, ... Institute of Electrical and Electronics Engineers (IEEE), 2023 | 1 | 2023 |
| DSbD CHERI and Morello Capability Essential IP (Version 1) RNM Watson, J Woodruff, A Joannou, SW Moore, P Sewell University of Cambridge, Computer Laboratory, 2020 | 1 | 2020 |
| Safe Speculation for CHERI F Fuchs, J Woodruff, P Rugg, A Joannou, J Clarke, J Baldwin, B Davis, ... | | 2024 |
| Advanced Dynamic Scalarisation for RISC-V GPGPUs M Naylor, A Joannou, AT Markettos, P Metzger, S Moore, T Jones | | 2024 |
| A Suite of Processors to Explore CHERI-RISC-V Microarchitecture P Rugg, J Woodruff, A Joannou, SW Moore | | 2024 |
| Architectural Contracts for Safe Speculation FA Fuchs, J Woodruff, P Rugg, M van der Mass, A Joannou, A Richardson, ... 2023 IEEE 41st International Conference on Computer Design (ICCD), 578-586, 2023 | | 2023 |
| Research data supporting'Cornucopia: Temporal Safety for CHERI Heaps' N Filardo, B Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, B Davis, H Xia, ... | | 2020 |
| Proving security properties of CHERI-MIPS K Nienhuis, A Joannou, P Sewell 25th Automated Reasoning Workshop, 18, 2018 | | 2018 |
