| High performance CMOS fabricated on hybrid substrate with different crystal orientations M Yang, M Ieong, L Shi, K Chan, V Chan, A Chou, E Gusev, K Jenkins, ... IEEE International Electron Devices Meeting 2003, 18.7. 1-18.7. 4, 2003 | 423 | 2003 |
| Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers V Chan, KW Guarini, M Ieong US Patent 6,821,826, 2004 | 304 | 2004 |
| Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers V Chan, K Guarini, M Ieong US Patent App. 10/914,433, 2005 | 292 | 2005 |
| Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing HS Yang, R Malik, S Narasimha, Y Li, R Divakaruni, P Agnello, S Allen, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 234 | 2004 |
| Hybrid-orientation technology (HOT): Opportunities and challenges M Yang, VWC Chan, KK Chan, L Shi, DM Fried, JH Stathis, AI Chou, ... IEEE Transactions on Electron Devices 53 (5), 965-978, 2006 | 221 | 2006 |
| High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering V Chan, R Rengarajan, N Rovedo, W Jin, T Hook, P Nguyen, J Chen, ... IEEE International Electron Devices Meeting 2003, 3.8. 1-3.8. 4, 2003 | 177* | 2003 |
| Increasing carrier mobility in NFET and PFET transistors on a common wafer V Chan, H Yang US Patent 6,939,814, 2005 | 118 | 2005 |
| Three dimensional CMOS devices and integrated circuits M Ieong, KW Guarini, V Chan, K Bernstein, R Joshi, J Kedzierski, ... Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003 …, 2003 | 106 | 2003 |
| High performance and low power transistors integrated in 65nm bulk CMOS technology Z Luo, A Steegen, M Eller, R Mann, C Baiocco, P Nguyen, L Kim, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 105 | 2004 |
| HERMES Core–A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing R Khaddam-Aljameh, M Stanisavljevic, JF Mas, G Karunaratne, ... 2021 Symposium on VLSI Circuits, 1-2, 2021 | 95 | 2021 |
| Material for contact etch layer to enhance device performance AB Chakravarti, S Narasimha, V Chan, J Holt, SN Chakravarti US Patent 7,001,844, 2006 | 78 | 2006 |
| Strain for CMOS performance improvement V Chan, K Rim, M Ieong, S Yang, R Malik, YW Teh, M Yang Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 …, 2005 | 78 | 2005 |
| Transistor scaling with novel materials M Ieong, V Narayanan, D Singh, A Topol, V Chan, Z Ren Materials today 9 (6), 26-31, 2006 | 72 | 2006 |
| HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs R Khaddam-Aljameh, M Stanisavljevic, JF Mas, G Karunaratne, M Brändli, ... IEEE Journal of Solid-State Circuits 57 (4), 1027-1038, 2022 | 69 | 2022 |
| FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 65 | 2016 |
| Integrated liquid crystal optical switch based on total internal reflection A Zhang, KT Chan, MS Demokan, VWC Chan, PCH Chan, HS Kwok, ... Applied Physics Letters 86 (21), 2005 | 63 | 2005 |
| Three dimensional CMOS integrated circuits on large grain polysilicon films VWC Chan, PCH Chan, M Chan International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No …, 2000 | 63 | 2000 |
| Fully on-chip MAC at 14 nm enabled by accurate row-wise programming of PCM-based weights and parallel vector-transport in duration-format P Narayanan, S Ambrogio, A Okazaki, K Hosokawa, H Tsai, A Nomura, ... IEEE Transactions on Electron Devices 68 (12), 6629-6636, 2021 | 61 | 2021 |
| Gate-induced-drain-leakage current in 45-nm CMOS technology X Yuan, JE Park, J Wang, E Zhao, DC Ahlgren, T Hook, J Yuan, ... IEEE Transactions on Device and Materials Reliability 8 (3), 501-508, 2008 | 60 | 2008 |
| On the integration of CMOS with hybrid crystal orientations M Yang, V Chan, SH Ku, M Ieong, L Shi, KK Chan, CS Murthy, RT Mo, ... Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 160-161, 2004 | 59 | 2004 |
