Lois Orosa
Lois Orosa
Senior Researcher
Verified email at inf.ethz.ch
Title
Cited by
Cited by
Year
D-RaNGe: Using commodity DRAM devices to generate true random numbers with low latency and high throughput
JS Kim, M Patel, H Hassan, L Orosa, O Mutlu
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
312019
FLIN: Enabling fairness and enhancing performance in modern NVMe solid state drives
A Tavakkol, M Sadrosadati, S Ghose, J Kim, Y Luo, Y Wang, NM Ghiasi, ...
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
292018
EDEN: enabling energy-efficient, high-performance deep neural network inference using approximate DRAM
S Koppula, L Orosa, AG Yağlıkçı, R Azizi, T Shahroodi, K Kanellopoulos, ...
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
242019
Pacman: Tolerating asymmetric data races with unintrusive hardware
S Qi, N Otsuki, LO Nogueira, A Muzahid, J Torrellas
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
242012
Reducing DRAM latency via charge-level-aware look-ahead partial restoration
Y Wang, A Tavakkol, L Orosa, S Ghose, NM Ghiasi, M Patel, JS Kim, ...
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
232018
Robust machine learning systems: Challenges, current trends, perspectives, and the road ahead
M Shafique, M Naseer, T Theocharides, C Kyrkou, O Mutlu, L Orosa, ...
IEEE Design & Test 37 (2), 30-57, 2020
142020
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques
JS Kim, M Patel, AG Yaglikci, H Hassan, R Azizi, L Orosa, O Mutlu
arXiv preprint arXiv:2005.13121, 2020
132020
AVPP: Address-first value-next predictor with value prefetching for improving the efficiency of load value prediction
L Orosa, R Azevedo, O Mutlu
ACM Transactions on Architecture and Code Optimization (TACO) 15 (4), 1-30, 2018
102018
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off
H Luo, T Shahroodi, H Hassan, M Patel, AG Yaglikci, L Orosa, J Park, ...
arXiv preprint arXiv:2005.12775, 2020
92020
FlexSig: Implementing flexible hardware signatures
L Orosa, E Antelo, JD Bruguera
ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-20, 2012
92012
ITAP: Idle-Time-Aware Power Management for GPU Execution Units
M Sadrosadati, SB Ehsani, H Falahati, R Ausavarungnirun, A Tavakkol, ...
ACM Transactions on Architecture and Code Optimization (TACO) 16 (1), 1-26, 2019
72019
FIGARO: Improving system performance via fine-grained In-DRAM data relocation and caching
Y Wang, L Orosa, X Peng, Y Guo, S Ghose, M Patel, JS Kim, JG Luna, ...
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020
52020
A Hardware Approach to Detect, Expose and Tolerate High Level Data Races
L Orosa, J Lourenco
2016 24th Euromicro International Conference on Parallel, Distributed, and …, 2016
32016
Evanesco: Architectural Support for Efficient Data Sanitization in Modern Flash-Based Storage Systems
M Kim, J Park, G Cho, Y Kim, L Orosa, O Mutlu, J Kim
Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020
22020
Dataplant: enhancing system security with low-cost in-DRAM value generation primitives
L Orosa, Y Wang, I Puddu, M Sadrosadati, K Razavi, J Gómez-Luna, ...
arXiv preprint arXiv:1902.07344, 2019
22019
Dataplant: in-DRAM security mechanisms for low-cost devices
L Orosa, Y Wang, I Puddu, M Sadrosadati, K Razavi, JGLH Hassan, ...
arxiv, 2019
22019
Architecting a computer with a full optical RAM
J Gonzalez, L Orosa, R Azevedo
2016 IEEE International Conference on Electronics, Circuits and Systems …, 2016
22016
A Hardware Approach for Detecting, Exposing and Tolerating High Level Atomicity Violations
L Orosa, J Lourenço
Workshop on Dependable Multicore and Transactional Memory Systems (DMTM), 2014
22014
A Cache Filtering Mechanism for Hardware Transactional Memory Systems Decoupled from Caches
L Orosa, E Antelo, J D. Bruguera
XX Jornadas de Paralelismo, 165-170, 2009
2*2009
WoLFRaM: Enhancing wear-leveling and fault tolerance in resistive memories using programmable address decoders
L Yavits, L Orosa, S Mahar, JD Ferreira, M Erez, R Ginosar, O Mutlu
2020 IEEE 38th International Conference on Computer Design (ICCD), 187-196, 2020
12020
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