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Juan Salamanca
Juan Salamanca
São Paulo State University (Unesp)
Verified email at bsc.es
Title
Cited by
Cited by
Year
Using Hardware-Transactional-Memory Support to Implement Thread-Level Speculation
J Salamanca, JN Amaral, G Araujo
IEEE Transactions on Parallel and Distributed Systems 29 (2), 466-480, 2018
232018
Evaluating and improving thread-level speculation in hardware transactional memories
J Salamanca, JN Amaral, G Araujo
2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2016
192016
Performance evaluation of thread-level speculation in off-the-shelf hardware transactional memories
J Salamanca, JN Amaral, G Araujo
European Conference on Parallel Processing, 607-621, 2017
72017
A Proposal for Supporting Speculation in the OpenMP taskloop Construct
J Salamanca, A Baldassin
OpenMP: Conquering the Full Hardware Spectrum: 15th International Workshop …, 2019
62019
Loop-Carried Dependence Verification in OpenMP
J Salamanca, L Mattos, G Araujo
International Workshop on OpenMP, 87-102, 2014
52014
Improving speculative taskloop in hardware transactional memory
J Salamanca, A Baldassin
International Workshop on OpenMP, 3-17, 2021
42021
Evaluating the Performance of Speculative DOACROSS Loop Parallelization with taskloop
J Salamanca, A Baldassin
2020 18th International Conference on High Performance Computing …, 2020
42020
Using hardware transactional memory to implement speculative privatization in OpenMP
J Salamanca, A Baldassin
Languages and Compilers for Parallel Computing: 33rd International Workshop …, 2020
32020
Doacross parallelization based on component annotation and loop-carried probability
L Mattos, D Cesar, J Salamanca, JPL de Carvalho, M Pereira, G Araujo
2018 30th International Symposium on Computer Architecture and High …, 2018
22018
Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP
J Salamanca, A Baldassin
International Workshop on OpenMP, 50-64, 2022
12022
Performance Comparison of Speculative Taskloop and OpenMP-for-Loop Thread-Level Speculation on Hardware Transactional Memory
J Salamanca
2022 21st International Symposium on Parallel and Distributed Computing …, 2022
12022
How to Efficiently Parallelize Irregular DOACROSS Loops Using Fine Granularity and OpenMP Tasks: The SPEC mcf Case
J Salamanca, A Baldassin
International Workshop on OpenMP, 81-96, 2023
2023
Thread-level speculation on hardware transactional memory architectures= Especulação de threads usando arquiteturas de memória transacional em hardware
JJS Guillén
University of Campinas, 2017
2017
Using Hardware Transactional Memory to Enable Speculative Trace Optimization
J Salamanca, JN Amaral, G Araujo
2015 International Symposium on Computer Architecture and High Performance …, 2015
2015
Intérprete para un lenguaje de programación orientado a objetos, con mecanismos de optimización y modificación dinámica de código
JJ Salamanca Guillén, RG Gómez Díaz
Pontificia Universidad Católica del Perú, 2012
2012
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