| Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip PY Chen, D Kadetotad, Z Xu, A Mohanty, B Lin, J Ye, S Vrudhula, J Seo, ... 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 854-859, 2015 | 85 | 2015 |
| Parallel architecture with resistive crosspoint array for dictionary learning acceleration D Kadetotad, Z Xu, A Mohanty, PY Chen, B Lin, J Ye, S Vrudhula, S Yu, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5 (2 …, 2015 | 63 | 2015 |
| Compact modeling of STT-MTJ devices Z Xu, C Yang, M Mao, KB Sutaria, C Chakrabarti, Y Cao Solid-State Electronics 102, 76-81, 2014 | 26 | 2014 |
| On-chip sparse learning acceleration with CMOS and resistive synaptic devices J Seo, B Lin, M Kim, PY Chen, D Kadetotad, Z Xu, A Mohanty, S Vrudhula, ... IEEE Transactions on Nanotechnology 14 (6), 969-979, 2015 | 24 | 2015 |
| Parallel programming of resistive cross-point array for synaptic plasticity Z Xu, A Mohanty, PY Chen, D Kadetotad, B Lin, J Ye, S Vrudhula, S Yu, ... Procedia Computer Science 41, 126-133, 2014 | 20 | 2014 |
| Hierarchical modeling of phase change memory for reliable design Z Xu, KB Sutaria, C Yang, C Chakrabarti, Y Cao 2012 IEEE 30th International Conference on Computer Design (ICCD), 115-120, 2012 | 18 | 2012 |
| Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning D Kadetotad, Z Xu, A Mohanty, PY Chen, B Lin, J Ye, S Vrudhula, S Yu, ... 2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings …, 2014 | 12 | 2014 |
| The stochastic loss of spikes in spiking neural P systems: Design and implementation of reliable arithmetic circuits Z Xu, M Cavaliere, P An, S Vrudhula, Y Cao Fundamenta Informaticae 134 (1-2), 183-200, 2014 | 12 | 2014 |
| Compact modeling of STT-MTJ for SPICE simulation Z Xu, KB Sutaria, C Yang, C Chakrabarti, Y Cao 2013 Proceedings of the European Solid-State Device Research Conference …, 2013 | 12 | 2013 |
| A low cost multi-tiered approach to improving the reliability of multi-level cell PRAM C Yang, Y Emre, Z Xu, H Chen, Y Cao, C Chakrabarti Journal of Signal Processing Systems 76 (2), 133-147, 2014 | 8 | 2014 |
| Improving efficiency in sparse learning with the feedforward inhibitory motif Z Xu, S Skorheim, M Tu, V Berisha, S Yu, J Seo, M Bazhenov, Y Cao Neurocomputing 267, 141-151, 2017 | 3 | 2017 |
| Low cost ECC schemes for improving the reliability of DRAM+ PRAMMAIN memory systems M Mao, C Yang, Z Xu, Y Cao, C Chakrabarti 2014 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2014 | 3 | 2014 |
| SPICE modeling of STT-RAM for resilient design Z Xu, K Sutaria, C Yang, C Chakrabarti, Y Cao Proc. 5th Int. MOS-AK/GSA Workshop, 2012 | 2 | 2012 |
| Algorithm and Hardware Co-design for Learning On-a-chip Z Xu Arizona State University, 2017 | 1 | 2017 |
| Hardware-efficient learning with feedforward inhibition Z Xu, PY Chen, J Seo, S Yu, Y Cao 2016 IEEE International Nanoelectronics Conference (INEC), 1-2, 2016 | 1 | 2016 |
| 19 HeterogeneousMemoryDesign C Yang, Z Xu, C Chakrabarti, Y Cao VLSI: Circuits for Emerging Applications 1 (10), 407, 2017 | | 2017 |
| Heterogeneous memory design C Yang, Z Xu, C Chakrabarti, Y Cao VLSI: Circuits for Emerging Applications, 407-427, 2017 | | 2017 |
| Compact Modeling of STT Compact Modeling of STT-MTJ Compact Modeling of STT Compact Modeling of STT-MTJ Compact Modeling of STT Compact Modeling of STT MTJ for SPICE Simulation Z Xu, K Sutaria, C Yang, C Chakrabarti, YK Cao | | |
Yu CaoProfessor of Electrical Engineering, Arizona State UniversityE-mail confirmado em asu.edu
