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Vassilis Papaefstathiou
Vassilis Papaefstathiou
Computer Science Department, University of Crete and FORTH-ICS
E-mail confirmado em csd.uoc.gr - Página inicial
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ASIST: architectural support for instruction set randomization
A Papadogiannakis, L Loutsis, V Papaefstathiou, S Ioannidis
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications …, 2013
712013
Memory-efficient 5D packet classification at 40 Gbps
I Papaefstathiou, V Papaefstathiou
IEEE INFOCOM 2007-26th IEEE International Conference on Computer …, 2007
572007
Ecoscale: Reconfigurable computing and runtime system for future exascale systems
I Mavroidis, I Papaefstathiou, L Lavagno, DS Nikolopoulos, D Koch, ...
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 696-701, 2016
552016
Prefetching and cache management using task lifetimes
V Papaefstathiou, MGH Katevenis, DS Nikolopoulos, D Pnevmatikatos
Proceedings of the 27th international ACM conference on International …, 2013
502013
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability
G Kalokerinos, V Papaefstathiou, G Nikiforos, S Kavadias, M Katevenis, ...
2009 International Symposium on Systems, Architectures, Modeling, and …, 2009
402009
Formic: Cost-efficient and scalable prototyping of manycore architectures
S Lyberis, G Kalokerinos, M Lygerakis, V Papaefstathiou, D Tsaliagkos, ...
2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012
312012
RADAR: Runtime-assisted dead region management for last-level caches
M Manivannan, V Papaefstathiou, M Pericas, P Stenstrom
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
272016
Hybrid2: Combining caching and migration in hybrid memory systems
E Vasilakis, V Papaefstathiou, P Trancoso, I Sourdis
2020 IEEE International Symposium on High Performance Computer Architecture …, 2020
252020
Modeling energy-performance tradeoffs in ARM big. LITTLE architectures
E Vasilakis, I Sourdis, V Papaefstathiou, A Psathakis, MGH Katevenis
2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017
182017
LLC-guided data migration in hybrid memory systems
E Vasilakis, V Papaefstathiou, P Trancoso, I Sourdis
2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2019
172019
Decoupled fused cache: Fusing a decoupled LLC with a DRAM cache
E Vasilakis, V Papaefstathiou, P Trancoso, I Sourdis
ACM Transactions on Architecture and Code Optimization (TACO) 15 (4), 1-23, 2019
172019
Efficient Remote Block-level I/O over an RDMA-capable NIC
M Marazakis, K Xinidis, V Papaefstathiou, A Bilas
Proceedings of the 20th annual international conference on Supercomputing …, 2006
172006
A systematic evaluation of emerging mesh-like cmp nocs
A Psathakis, V Papaefstathiou, N Chrysos, F Chaix, E Vasilakis, ...
2015 ACM/IEEE Symposium on Architectures for Networking and Communications …, 2015
162015
Explicit communication and synchronization in SARC
M Katevenis, V Papaefstathiou, S Kavadias, D Pnevmatikatos, F Silla, ...
IEEE micro 30 (5), 30-41, 2010
162010
Odd-ecc: on-demand dram error correcting codes
A Malek, E Vasilakis, V Papaefstathiou, P Trancoso, I Sourdis
Proceedings of the International Symposium on Memory Systems, 96-111, 2017
152017
DDRNoC: Dual Data-Rate Network-on-Chip
A Ejaz, V Papaefstathiou, I Sourdis
ACM Transactions on Architecture and Code Optimization (TACO) 15 (2), 25, 2018
142018
Implementation and impact of an ultra-compact multi-FPGA board for large system prototyping
F Chaix, A Ioannou, N Kossifidis, N Dimou, G Ieronymakis, M Marazakis, ...
2019 IEEE/ACM International Workshop on Heterogeneous High-performance …, 2019
122019
FreewayNoC: A DDR NoC with pipeline bypassing
A Ejaz, V Papaefstathiou, I Sourdis
2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2018
112018
Profess: A probabilistic hybrid main memory management framework for high performance and fairness
D Knyaginin, V Papaefstathiou, P Stenstrom
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
112018
SLOOP: QoS-supervised loop execution to reduce energy on heterogeneous architectures
MW Azhar, P Stenström, V Papaefstathiou
ACM Transactions on Architecture and Code Optimization (TACO) 14 (4), 1-25, 2017
112017
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