| Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ... 2017 symposium on VLSI technology, T230-T231, 2017 | 768 | 2017 |
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| A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates S Zafar, Y Kim, V Narayanan, C Cabral, V Paruchuri, B Doris, J Stathis, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 23-25, 2006 | 285 | 2006 |
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| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 174 | 2016 |
| Hafnium oxide gate dielectrics on sulfur-passivated germanium MM Frank, SJ Koester, M Copel, JA Ott, VK Paruchuri, H Shang, ... Applied physics letters 89 (11), 2006 | 174 | 2006 |
| A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ... 2011 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2011 | 129 | 2011 |
| Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for cmos NA Bojarczuk, MP Chudzik, MW Copel, S Guha, R Jammy, V Narayanan, ... US Patent App. 12/166,690, 2008 | 123 | 2008 |
| Examination of flatband and threshold voltage tuning of HfO2∕ TiN field effect transistors by dielectric cap layers S Guha, VK Paruchuri, M Copel, V Narayanan, YY Wang, PE Batson, ... Applied physics letters 90 (9), 2007 | 122 | 2007 |
| High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, ... 2007 IEEE symposium on VLSI technology, 194-195, 2007 | 119 | 2007 |
| A 0.063 µm2FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch VS Basker, T Standaert, H Kawasaki, CC Yeh, K Maitra, T Yamashita, ... 2010 Symposium on VLSI Technology, 19-20, 2010 | 118 | 2010 |
| Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond F Andrieu, O Weber, J Mazurier, O Thomas, JP Noel, ... 2010 Symposium on VLSI Technology, 57-58, 2010 | 112 | 2010 |
| Metal gate CMOS with at least a single gate metal and dual gate dielectrics BB Doris, YH Kim, BP Linder, V Narayanan, VK Paruchuri US Patent 7,432,567, 2008 | 111 | 2008 |
| Band-edge high-performance high-k/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond TC Chen, G Shahidi, S Guha, M Ieong, MP Chudzik, R Jammy, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 178-179, 2006 | 109 | 2006 |
| Role of oxygen vacancies in V/sub FB//V/sub t/stability of pFET metals on HfO/sub 2 E Cartier, FR McFeely, V Narayanan, P Jamison, BP Linder, M Copel, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 230-231, 2005 | 109 | 2005 |
| A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 108 | 2014 |
| High performance CMOS circuits, and methods for fabricating the same J Arnold, G Biery, A Callegari, TC Chen, M Chudzik, B Doris, M Gribelyuk, ... US Patent App. 11/323,578, 2007 | 107 | 2007 |
| Fundamental understanding and optimization of PBTI in nFETs with SiO2/HfO2 gate stack E Cartier, BP Linder, V Narayanan, VK Paruchuri 2006 International Electron Devices Meeting, 1-4, 2006 | 103 | 2006 |
| 22 nm technology compatible fully functional 0.1 μm26T-SRAM cell BS Haran, A Kumar, L Adam, J Chang, V Basker, S Kanakasabapathy, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 96 | 2008 |
| Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics NA Bojarczuk Jr, C Cabral Jr, EA Cartier, MW Copel, MM Frank, ... US Patent 7,105,889, 2006 | 94 | 2006 |
