Niranjan Kulkarni
Niranjan Kulkarni
Cadence Design Systems, Arizona State University
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Identification of threshold functions and synthesis of threshold networks
T Gowda, S Vrudhula, N Kulkarni, K Berezowski
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
Reducing power, leakage, and area of standard-cell asics using threshold logic flip-flops
N Kulkarni, J Yang, JS Seo, S Vrudhula
IEEE transactions on very large scale integration (VLSI) systems 24 (9 …, 2016
Spintronic threshold logic array (STLA)—A compact, low leakage, non-volatile gate array architecture
NS Nukala, N Kulkarni, S Vrudhula
Journal of Parallel and Distributed Computing 74 (6), 2452-2460, 2014
Design of a robust, high performance standard cell threshold logic family for DSM technology
S Leshner, N Kulkarni, S Vrudhula, K Berezowski
2010 International Conference on Microelectronics, 52-55, 2010
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation
J Yang, N Kulkarni, S Yu, S Vrudhula
2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2014
Threshold gate and threshold logic array
S Vrudhula, NS Nukala, N Kulkarni
US Patent 9,306,151, 2016
Minimizing area and power of sequential cmos circuits using threshold decomposition
N Kulkarni, N Nukala, S Vrudhula
Proceedings of the International Conference on Computer-Aided Design, 605-612, 2012
Design of threshold logic gates using emerging devices
S Vrudhula, N Kulkami, J Yang
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 373-376, 2015
Technology mapping for threshold and logic gate hybrid circuits
S Vrudhula, N Kulkarni
US Patent 8,832,614, 2014
Method of obfuscating digital logic circuits using threshold voltage
S Vrudhula, A Dengi, N Kulkarni, J Davis
US Patent 9,876,503, 2018
Digital IP protection using threshold voltage control
J Davis, N Kulkarni, J Yang, A Dengi, S Vrudhula
2016 17th International Symposium on Quality Electronic Design (ISQED), 344-349, 2016
Dynamic and leakage power reduction of ASICs using configurable threshold logic gates
J Yang, J Davis, N Kulkarni, J Seo, S Vrudhula
2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015
A fast, energy efficient, field programmable threshold-logic array
N Kulkarni, J Yang, S Vrudhula
2014 International Conference on Field-Programmable Technology (FPT), 300-305, 2014
Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs
S Vrudhula, A Dengi, N Kulkarni
US Patent 10,551,869, 2020
Threshold logic gates with resistive networks
S Vrudhula, J Yang, N Kulkarni, S Yu
US Patent 9,356,598, 2016
Fast and robust differential flipflops and their extension to multi-input threshold gates
J Yang, N Kulkarni, J Davis, S Vrudhula
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 822-825, 2015
Threshold logic element with stabilizing feedback
S Vrudhula, N Kulkarni
US Patent 9,473,139, 2016
Energy efficient, robust differential mode d-flip-flop
S Vrudhula, N Kulkarni, J Yang
US Patent 10,250,236, 2019
Robust, low power, reconfigurable threshold logic array
S Vrudhula, N Kulkarni
US Patent 9,490,815, 2016
Efficient enumeration of unidirectional cuts for technology mapping of Boolean networks
N Kulkarni, S Vrudhula
arXiv preprint arXiv:1603.07371, 2016
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