| The ArchC architecture description language and tools R Azevedo, S Rigo, M Bartholomeu, G Araujo, C Araujo, E Barros International Journal of Parallel Programming 33 (5), 453-484, 2005 | 184 | 2005 |
| A method for partitioning UNITY language in hardware and software E Barros, W Rosenstiel, X Xiong Proc. EuroDAC 94, 220-225, 1994 | 125 | 1994 |
| A petri net model for hardware/software codesign P Maciel, E Barros, W Rosenstiel Design Automation for Embedded Systems 4 (4), 243-310, 1999 | 61 | 1999 |
| Extreme value theory for estimating task execution time bounds: A careful look G Lima, D Dias, E Barros 2016 28th Euromicro Conference on Real-Time Systems (ECRTS), 200-211, 2016 | 54 | 2016 |
| A method for hardware software partitioning E Barros, W Rosenstiel 1992 Proceedings Computer Systems and Software Engineering, 580,581,582,583 …, 1992 | 46 | 1992 |
| Hardware/software partitioning with UNITY E Barros, W Rosenstiel, X Xiong Proc. 2nd International Workshop on Hardware-Software Codesign, 1993 | 45 | 1993 |
| A one-shot configurable-cache tuner for improved energy and performance A Gordon-Ross, P Viana, F Vahid, W Najjar, E Barros 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 43 | 2007 |
| Towards provably correct hardware/software partitioning using OCCAM E Barros, A Sampaio Third International Workshop on Hardware/Software Codesign, 210-217, 1994 | 41 | 1994 |
| A normal form reduction strategy for hardware/software partitioning L Silva, A Sampaio, E Barros International Symposium of Formal Methods Europe, 624-643, 1997 | 38 | 1997 |
| Hardware/Software partitioning using UNITY E da Barros | 36 | 1993 |
| Exploring memory hierarchy with ArchC P Viana, E Barros, S Rigo, R Azevedo, G Araújo Proceedings. 15th Symposium on Computer Architecture and High Performance …, 2003 | 34 | 2003 |
| Configurable cache subsetting for fast cache tuning P Viana, A Gordon-Ross, E Keogh, E Barros, F Vahid 2006 43rd ACM/IEEE Design Automation Conference, 695-700, 2006 | 33 | 2006 |
| A table-based method for single-pass cache optimization P Viana, A Gordon-Ross, E Barros, F Vahid Proceedings of the 18th ACM Great Lakes symposium on VLSI, 71-76, 2008 | 25 | 2008 |
| A safe, accurate intravenous infusion control system E Barros, MVD des Santos Ieee Micro 18 (5), 12-21, 1998 | 24 | 1998 |
| A constructive approach to hardware/software partitioning L Silva, A Sampaio, E Barros Formal Methods in System Design 24 (1), 45-90, 2004 | 23 | 2004 |
| Hardware/Software co-design: projetando hardware e software concorrentemente E Barros, S Cavalcante, ME de Lima, C Valderrama IME-USP, 2000 | 22 | 2000 |
| Silicon validated ip cores designed by the brazil-ip network AK Rocha, P Lira, YY Ju, E Barros, E Melcher, G Araujo IP/SOC 2006, 142-147, 2006 | 19 | 2006 |
| Platform designer: An approach for modeling multiprocessor platforms based on SystemC C Araujo, M Gomes, E Barros, S Rigo, R Azevedo, G Araujo Design Automation for Embedded Systems 10 (4), 253-283, 2005 | 19 | 2005 |
| A computational reflection mechanism to support platform debugging in SystemC B Albertini, S Rigo, G Araujo, C Araujo, E Barros, W Azevedo Proceedings of the 5th IEEE/ACM international conference on Hardware …, 2007 | 18 | 2007 |
| ipPROCESS: A Development Process for Soft IP-core with Prototyping in FPGA M Lima, F Santos, J Bione, T Lins, E Barros Forum on Design Languages (FDL 2005), Swiss, 2005 | 16 | 2005 |
