Dhruva Ghai
Dhruva Ghai
Professor, Oriental University, Indore, India
Verified email at orientaluniversity.in - Homepage
Title
Cited by
Cited by
Year
Design of parasitic and process-variation aware nano-CMOS RF circuits: A VCO case study
D Ghai, SP Mohanty, E Kougianos
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (9 …, 2009
712009
Comparative analysis of double gate FinFET configurations for analog circuit design
D Ghai, SP Mohanty, G Thakral
2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013
292013
Parasitic aware process variation tolerant voltage controlled oscillator (VCO) design
D Ghai, SP Mohanty, E Kougianos
9th International Symposium on Quality Electronic Design (isqed 2008), 330-333, 2008
182008
A 45nm flash analog to digital converter for low voltage high speed system on chips
D Ghai, SP Mohanty, E Kougianos
Proceedings of the 13th NASA Symposium on VLSI Design 3, 2007
162007
Novel intrusion detection and prevention for mobile ad hoc networks: A single-and multiattack case study
G Vaseer, G Ghai, D Ghai
IEEE Consumer Electronics Magazine 8 (3), 35-39, 2019
132019
Fast optimization of nano-CMOS voltage-controlled oscillator using polynomial regression and genetic algorithm
D Ghai, SP Mohanty, G Thakral
Microelectronics Journal 44 (8), 631-641, 2013
122013
A combined DOE-ILP based power and read stability optimization in nano-CMOS SRAM
G Thakral, SP Mohanty, D Ghai, DK Pradhan
2010 23rd International Conference on VLSI Design, 45-50, 2010
122010
A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs
D Ghai, SP Mohanty, E Kougianos
9th International Symposium on Quality Electronic Design (isqed 2008), 257-260, 2008
112008
Process variation analysis and optimization of a FinFET-based VCO
VP Yanambaka, SP Mohanty, E Kougianos, D Ghai, G Ghai
IEEE Transactions on Semiconductor Manufacturing 30 (2), 126-134, 2017
102017
Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case study
D Ghai, SP Mohanty, G Thakral
International Symposium on Quality Electronic Design (ISQED), 406-411, 2013
102013
P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP
G Thakral, SP Mohanty, D Ghai, DK Pradhan
2010 11th International Symposium on Quality Electronic Design (ISQED), 176-183, 2010
102010
A PVT aware accurate statistical logic library for high-κ metal-gate nano-CMOS
D Ghai, SP Mohanty, E Kougianos, P Patra
2009 10th International Symposium on Quality Electronic Design, 47-54, 2009
102009
Interdependency study of process and design parameter scaling for power optimization of nano-CMOS circuits under process variation
SP Mohanty, E Kougianos, D Ghai, P Patra
Proceedings of the 16th ACM/IEEE International Workshop on Logic and …, 2007
102007
Double gate FinFET based mixed-signal design: A VCO case study
D Ghai, SP Mohanty, G Thakral
2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013
92013
Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments
D Ghai, SP Mohanty, E Kougianos
2009 10th International Symposium on Quality Electronic Design, 172-178, 2009
92009
A neighbor trust-based mechanism to protect mobile networks
G Vaseer, G Ghai, D Ghai, PS Patheja
IEEE potentials 38 (1), 20-25, 2018
72018
A universal level converter towards the realization of energy efficient implantable drug delivery nano-electro-mechanical-systems
SP Mohanty, D Ghai, E Kougianos, B Joshi
2009 10th International Symposium on Quality Electronic Design, 673-679, 2009
72009
A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO
SP Mohanty, D Ghai, E Kougianos
2010 23rd International Conference on VLSI Design, 99-104, 2010
62010
Unified P4 (power-performance-process-parasitic) fast optimization of a nano-CMOS VCO
D Ghai, SP Mohanty, E Kougianos
Proceedings of the 19th ACM Great Lakes symposium on VLSI, 303-308, 2009
52009
A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM
G Thakral, SP Mohanty, D Ghai, DK Pradhan
Proceedings of the 20th symposium on Great lakes symposium on VLSI, 323-328, 2010
42010
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