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Phillip Restle
Phillip Restle
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When are transmission-line effects important for on-chip interconnections?
A Deutsch, GV Kopcsay, PJ Restle, HH Smith, G Katopis, WD Becker, ...
IEEE Transactions on microwave theory and techniques 45 (10), 1836-1846, 1997
4911997
A clock distribution network for microprocessors
PJ Restle, TG McNamara, DA Webber, PJ Camporese, KF Eng, ...
IEEE Journal of Solid-State Circuits 36 (5), 792-799, 2001
3802001
SiGe-channel heterojunction p-MOSFET's
S Verdonckt-Vandebroek, EF Crabbe, BS Meyerson, DL Harame, ...
IEEE Transactions on Electron Devices 41 (1), 90-101, 1994
3751994
On-chip wiring design challenges for gigahertz operation
A Deutsch, PW Coteus, GV Kopcsay, HH Smith, CW Surovic, BL Krauter, ...
Proceedings of the IEEE 89 (4), 529-555, 2001
2762001
A new'shift and ratio'method for MOSFET channel-length extraction
Y Taur, DS Zicherman, DR Lombardi, PJ Restle, CH Hsu, HI Nanafi, ...
IEEE Electron Device Letters 13 (5), 267-269, 1992
2541992
The circuit and physical design of the POWER4 microprocessor
JD Warnock, JM Keaty, J Petrovick, JG Clabes, CJ Kircher, BL Krauter, ...
IBM Journal of Research and Development 46 (1), 27-51, 2002
2222002
Design and implementation of the POWER5™ microprocessor
J Clabes, J Friedrich, M Sweet, J DiLullo, S Chu, D Plass, J Dawson, ...
Proceedings of the 41st annual Design Automation Conference, 670-672, 2004
1952004
Physical design of a fourth-generation POWER GHz microprocessor
CJ Anderson, J Petrovick, JM Keaty, J Warnock, G Nussbaum, JM Tendier, ...
2001 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2001
1522001
Designing the best clock distribution network
PJ Restle, A Deutsch
1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No …, 1998
1421998
DRAM variable retention time
Restle, Park, Lloyd
1992 International Technical Digest on Electron Devices Meeting, 807-810, 1992
1391992
XY grid tree clock distribution network with tunable tree and grid networks
PJ Camporese, A Deutsch, TG McNamara, PJ Restle, DA Webber
US Patent 6,311,313, 2001
1382001
Design and experimental technology for 0.1-µm gate-length low-temperature operation FET's
GA Sai-Halasz, MR Wordeman, DP Kern, E Ganin, S Rishton, ...
IEEE Electron Device Letters 8 (10), 463-466, 1987
1351987
High performance 0.25 mu m p-MOSFETs with silicon-germanium channels for 300 K and 77 K operation
VP Kesan, S Subbana, PJ Restle, MJ Tejwani, JM Aitken, SS Iyer, JA Ott
International Electron Devices Meeting 1991 [Technical Digest], 25-28, 1991
1341991
High-mobility modulation-doped SiGe-channel p-MOSFETs
S Verdonckt-Vandebroek, EF Crabbe, BS Meyerson, DL Harame, ...
IEEE Electron Device Letters 12 (8), 447-449, 1991
1331991
Full-wave PEEC time-domain method for the modeling of on-chip interconnects
PJ Restle, AE Ruehli, SG Walker, G Papadopoulos
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001
1272001
Gradient-based optimization of custom circuits using a static-timing formulation
AR Conn, IM Elfadel, WW Molzen Jr, PR O'brien, PN Strenski, ...
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 452-459, 1999
1271999
Uniform-phase uniform-amplitude resonant-load global clock distributions
SC Chan, KL Shepard, PJ Restle
IEEE Journal of Solid-State Circuits 40 (1), 102-109, 2005
1212005
5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth
EJ Fluhr, J Friedrich, D Dreps, V Zyuban, G Still, C Gonzalez, A Hall, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
1202014
A 4.6 GHz resonant global clock distribution network
SC Chan, PJ Restle, KL Shepard, NK James, RL Franch
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004
1162004
On-chip timing uncertainty measurements on IBM microprocessors
R Franch, P Restle, N James, W Huott, J Friedrich, R Dixon, S Weitzel, ...
2007 IEEE International Test Conference, 1-7, 2007
1112007
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