| Programmable packet scheduling at line rate A Sivaraman, S Subramanian, M Alizadeh, S Chole, ST Chuang, ... Proceedings of the 2016 ACM SIGCOMM Conference, 44-57, 2016 | 311 | 2016 |
| drmt: Disaggregated programmable switching S Chole, A Fingerhut, S Ma, A Sivaraman, S Vargaftik, A Berger, ... Proceedings of the Conference of the ACM Special Interest Group on Data …, 2017 | 184 | 2017 |
| Towards programmable packet scheduling A Sivaraman, S Subramanian, A Agrawal, S Chole, ST Chuang, T Edsall, ... Proceedings of the 14th ACM workshop on hot topics in networks, 1-7, 2015 | 72 | 2015 |
| Methods and Apparatus for Constructing Digital Circuits for Performing Matrix Operations SCH Ma, ST Chuang, SV Chole US Patent App. 16/377,103, 2020 | 4 | 2020 |
| Method And Apparatus For Scheduling Matrix Operations In Digital Processing Systems ST Chuang, SV Chole, SCH Ma US Patent App. 16/869,520, 2020 | 3 | 2020 |
| Methods and Apparatus for Constructing Digital Circuits for Performing Matrix Operations SV Chole, ST Chuang, SCH Ma US Patent App. 16/149,054, 2020 | 2 | 2020 |
| SparseCore: An accelerator for structurally sparse CNNs S Chole, R Tadishetti, S Reddy Proc. SysML Conf, 1-3, 2018 | 2 | 2018 |
| Methods and Apparatus for Accessing External Memory in a Neural Network Processing System S Ma, ST Chuang, S Chole US Patent App. 17/848,316, 2023 | | 2023 |
| Method and apparatus for efficiently processing convolution neural network operations ST Chuang, SV Chole, SCH Ma US Patent 11,151,416, 2021 | | 2021 |
| Dynamic packet buffers with consolidation of low utilized memory banks SV Chole, ST Chuang, G Akis, F Bonardi, R Pan US Patent 9,965,211, 2018 | | 2018 |
| dRMT: Disaggregated Programmable Switching (Extended Version) S Chole, A Fingerhut, S Ma, A Sivaraman, S Vargaftik, A Berger, ... | | |
