Modeling process variability in scaled CMOS technology SK Saha
IEEE Design & Test of Computers 27 (2), 8-16, 2010
200 2010 Semiconductor structure having two levels of buried regions DR Farrenkopf, RB Merrill, S Saha, KE Brehmer, K Gadepally, ...
US Patent 5,889,315, 1999
188 1999 Fabrication of semiconductor structure having two levels of buried regions DR Farrenkopf, RB Merrill, S Saha, KE Brehmer, K Gadepally, ...
US Patent 5,899,714, 1999
166 1999 Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features H Van Tran, S Saha
US Patent 8,385,147, 2013
114 2013 Compact MOSFET Modeling for Process Variability-Aware VLSI Circuit Design SK Saha
IEEE Access 2, 104-115, 2014
100 2014 MOSFET test structures for two-dimensional device simulation S Saha
Solid-state electronics 38 (1), 69-73, 1995
78 1995 Subthreshold analog/RF performance enhancement of underlap DG FETs with high-k spacer for low power applications K Koley, A Dutta, B Syamal, SK Saha, CK Sarkar
IEEE Transactions on Electron Devices 60 (1), 63-69, 2012
67 2012 Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond SK Saha
CRC Press, Taylor & Francis Group, 2015
59 2015 Design considerations for sub-90-nm split-gate flash-memory cells SK Saha
IEEE Transactions on Electron Devices 54 (11), 3049-3055, 2007
55 2007 Technology computer aided design C Sarkar
CRC Press, 2018
49 2018 Analysis of High- Spacer Asymmetric Underlap DG-MOSFET for SOC Application K Koley, A Dutta, SK Saha, CK Sarkar
IEEE Transactions on Electron Devices 62 (6), 1733-1738, 2015
45 2015 Design considerations for 25 nm MOSFET devices S Saha
Solid-State Electronics 45 (10), 1851-1857, 2001
45 2001 Efficient III-Nitride MIS-HEMT devices with high-κ gate dielectric for high-power switching boost converter circuits A Mohanbabu, N Mohankumar, DG Raj, P Sarkar, SK Saha
Superlattices and Microstructures 103, 270-284, 2017
44 2017 Scaling considerations for high performance 25 nm metal–oxide–semiconductor field effect transistors S Saha
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2001
36 2001 Impact ionization rate of electrons for accurate simulation of substrate current in submicron devices S Saha, CS Yeh, B Gadepally
Solid-state electronics 36 (10), 1429-1432, 1993
36 1993 Managing technology CAD for competitive advantage: An efficient approach for integrated circuit fabrication technology development SK Saha
IEEE Transactions on Engineering Management 46 (2), 221-229, 1999
35 1999 Introduction to technology computer aided design SK Saha
Technology Computer Aided Design, 17-60, 2018
30 2018 Effects of inversion layer quantization on channel profile engineering for nMOSFETs with 0.1 μm channel lengths S Saha
Solid-State Electronics 42 (11), 1985-1991, 1998
30 1998 FinFET Devices for VLSI Circuits and Systems SK Saha
CRC Press Taylor and Francis Group, 2020
26 2020 Transistors having optimized source-drain structures and methods for making the same SK Saha
US Patent 6,344,405, 2002
25 2002