Marcelo Lubaszewski
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A scalable test strategy for network-on-chip routers
AM Amory, E Brião, É Cota, M Lubaszewski, FG Moraes
IEEE International Conference on Test, 2005., 9 pp.-599, 2005
The impact of NoC reuse on the testing of core-based systems
É Cota, M Kreutz, CA Zeferino, L Carro, M Lubaszewski, A Susin
Proceedings. 21st VLSI Test Symposium, 2003., 128-133, 2003
Power-aware NoC Reuse on the Testing of Core-based Systems.
E Cota, L Carro, F Wagner, M Lubaszewski
International Test Conference, 612-621, 2003
Reliability, Availability and Serviceability of Networks-on-chip
É Cota, A de Morais Amory, MS Lubaszewski
Springer Science & Business Media, 2011
Reusing an on-chip network for the test of core-based systems
É Cota, L Carro, M Lubaszewski
ACM Transactions on Design Automation of Electronic Systems (TODAES) 9 (4 …, 2004
A high-fault-coverage approach for the test of data, control and handshake interconnects in mesh networks-on-chip
E Cota, FL Kastensmidt, M Cassel, M Herve, P Almeida, P Meirelles, ...
IEEE Transactions on Computers 57 (9), 1202-1215, 2008
Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets
S Mir, M Lubaszewski, B Courtois
Journal of Electronic Testing 9 (1), 43-57, 1996
A reliable fail-safe system
M Lubaszewski, B Courtois
IEEE Transactions on Computers 47 (2), 236-241, 1998
Wrapper design for the reuse of networks-on-chip as test access mechanism
AM Amory, K Goossens, EJ Marinissen, M Lubaszewski, F Moraes
Eleventh IEEE European Test Symposium (ETS'06), 213-218, 2006
Design of self-checking fully differential circuits and boards
M Lubaszewski, S Mir, V Kolarik, C Nielsen, B Courtois
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (2), 113-128, 2000
Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism
AM Amory, K Goossens, EJ Marinissen, M Lubaszewski, F Moraes
IET Computers & Digital Techniques 1 (3), 197-206, 2007
Designing self-exercising analogue checkers
V Kolarik, M Lubaszewski, B Courtois
Proceedings of IEEE VLSI Test Symposium, 252-257, 1994
Improving yield of torus NoCs through fault-diagnosis-and-repair of interconnect faults
C Concatto, P Almeida, F Kastensmidt, E Cota, M Lubaszewski, M Herve
2009 15th IEEE International On-Line Testing Symposium, 61-66, 2009
Unified built-in self-test for fully differential analog circuits
S Mir, M Lubaszewski, B Courtois
Journal of Electronic Testing 9 (1), 135-151, 1996
Fault detection, diagnosis and prediction in electrical valves using self-organizing maps
LF Gonçalves, JL Bosa, TR Balen, MS Lubaszewski, EL Schneider, ...
Journal of Electronic Testing 27 (4), 551-564, 2011
A new adaptive analog test and diagnosis system
EF Cota, M Negreiros, L Carro, M Lubaszewski
IEEE Transactions on Instrumentation and Measurement 49 (2), 223-227, 2000
Designing a radiation hardened 8051-like micro-controller
FG de Lima, E Cota, L Carro, M Lubaszewski, R Reis, R Velazco, ...
Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat …, 2000
Microsystems testing: an approach and open problems
M Lubaszewski, ÉF Cota, B Courtois
Proceedings of the conference on Design, automation and test in Europe, 524-529, 1998
Analog checkers with absolute and relative tolerances
V Kolarik, S Mir, M Lubaszewski, B Courtois
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1995
Frequency-based BIST for analog circuit testing
S Khaled, B Kaminska, B Courtois, M Lubaszewski
Proceedings 13th IEEE VLSI Test Symposium, 54-59, 1995
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