Cryogenic subthreshold swing saturation in FD-SOI MOSFETs described with band broadening H Bohuslavskyi, AGM Jansen, S Barraud, V Barral, M Cassé, L Le Guevel, ...
IEEE Electron Device Letters 40 (5), 784-787, 2019
122 2019 Cryogenic temperature characterization of a 28-nm FD-SOI dedicated structure for advanced CMOS and quantum technologies co-integration P Galy, JC Lemyre, P Lemieux, F Arnaud, D Drouin, M Pioro-Ladriere
IEEE Journal of the Electron Devices Society 6, 594-600, 2018
92 2018 A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters S Cristoloveanu, KH Lee, MS Parihar, H El Dirani, J Lacord, S Martinie, ...
Solid-State Electronics 143, 10-19, 2018
58 2018 28nm Fully-depleted SOI technology: Cryogenic control electronics for quantum computing H Bohuslavskyi, S Barraud, M Cassé, V Barrai, B Bertrand, L Hutin, ...
2017 Silicon Nanoelectronics Workshop (SNW), 143-144, 2017
55 2017 Variability evaluation of 28nm FD-SOI technology at cryogenic temperatures down to 100mK for quantum computing BC Paz, L Le Guevel, M Casse, G Billiot, G Pillonnet, AGM Jansen, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
48 2020 Extended Analysis of the C Navarro, J Lacord, MS Parihar, F Adamu-Lema, M Duan, N Rodriguez, ...
IEEE Transactions on Electron Devices 64 (11), 4486-4491, 2017
45 2017 First demonstration of a full 28nm high-k/metal gate circuit transfer from Bulk to UTBB FDSOI technology through hybrid integration D Golanski, P Fonteneau, C Fenouillet-Beranger, A Cros, F Monsieur, ...
2013 Symposium on VLSI Circuits, T124-T125, 2013
40 2013 Cryogenic characterization of 28-nm FD-SOI ring oscillators with energy efficiency optimization H Bohuslavskyi, S Barraud, V Barral, M Cassé, L Le Guevel, L Hutin, ...
IEEE Transactions on Electron Devices 65 (9), 3682-3688, 2018
35 2018 C Navarro, M Duan, MS Parihar, F Adamu-Lema, S Coseman, J Lacord, ...
IEEE Transactions on Electron Devices 64 (12), 4904-4909, 2017
35 2017 Electronic device, in particular for protection against electrostatic discharges, and method for protecting a component against electrostatic discharges J Bourgeat, C Entringer, P Galy, J Jimenez
US Patent 9,019,666, 2015
33 2015 Experimental Demonstration of Operational Z2 -FET Memory Matrix S Navarro, C Navarro, C Marquez, H El Dirani, P Galy, M Bawedin, ...
IEEE Electron Device Letters 39 (5), 660-663, 2018
32 2018 Evidence of supercoupling effect in ultrathin silicon layers using a four-gate MOSFET S Cristoloveanu, S Athanasiou, M Bawedin, P Galy
IEEE Electron Device Letters 38 (2), 157-159, 2016
32 2016 Structure for protecting an integrated circuit against electrostatic discharges P Galy, C Entringer, J Bourgeat
US Patent 8,331,069, 2012
31 2012 BIMOS transistor and its applications in ESD protection in advanced CMOS technology P Galy, J Jimenez, J Bourgeat, A Dray, G Troussier, B Heitz, N Guitard, ...
2012 IEEE International Conference on IC Design & Technology, 1-4, 2012
31 2012 Front and back channels coupling and transport on 28 nm FD-SOI MOSFETs down to liquid-He temperature BC Paz, M Cassé, S Haendler, A Juge, E Vincent, P Galy, F Arnaud, ...
Solid-State Electronics 186, 108071, 2021
24 2021 Evidence of 2D intersubband scattering in thin film fully depleted silicon-on-insulator transistors operating at 4.2 K M Cassé, B Cardoso Paz, G Ghibaudo, T Poiroux, E Vincent, P Galy, ...
Applied Physics Letters 116 (24), 2020
22 2020 Experimental investigation of ESD design window for fully depleted SOI N-MOSFETs T Benoist, C Fenouillet-Beranger, P Perreau, C Buj, P Galy, ...
Microelectronic Engineering 88 (7), 1276-1279, 2011
22 2011 Local ESD protection structure based on silicon controlled rectifier achieving very low overshoot voltage J Bourgeat, C Entringer, P Galy, P Fonteneau, M Bafleur
2009 31st EOS/ESD Symposium, 1-8, 2009
21 2009 Robust technology computer-aided design of gated quantum dots at cryogenic temperature F Beaudoin, P Philippopoulos, C Zhou, I Kriekouki, M Pioro-Ladrière, ...
Applied physics letters 120 (26), 2022
20 2022 ESD design challenges in 28nm hybrid FDSOI/Bulk advanced CMOS process A Dray, N Guitard, P Fonteneau, D Golanski, C Fenouillet-Beranger, ...
Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2012, 1-7, 2012
19 2012 
Francisco GamizProfessor of ElectronicsE-mail confirmado em ugr.es
