Wei Cao
Wei Cao
Postdoc Researcher, ECE@UCSB
E-mail confirmado em ucsb.edu
Citado por
Citado por
A subthermionic tunnel field-effect transistor with an atomically thin channel
D Sarkar, X Xie, W Liu, W Cao, J Kang, Y Gong, S Kraemer, PM Ajayan, ...
Nature 526 (7571), 91-95, 2015
2D Semiconductor FETs--Projections and Design for Sub-10 nm VLSI
W Cao, J Kang, D Sarkar, W Liu, K Banerjee
Electron Devices, IEEE Transactions on 62 (11), 3459-3469, 2015
Impact of Contact on the Operation and Performance of Back-Gated Monolayer MoS2 Field-Effect-Transistors
W Liu, D Sarkar, J Kang, W Cao, K Banerjee
Acs Nano 9 (8), 7904-7912, 2015
A compact current–voltage model for 2D semiconductor based field-effect transistors considering interface traps, mobility degradation, and inefficient doping effect
W Cao, J Kang, W Liu, K Banerjee
IEEE Transactions on Electron Devices 61 (12), 4282-4290, 2014
High-performance few-layer-MoS2 field-effect-transistor with record low contact-resistance
W Liu, J Kang, W Cao, D Sarkar, Y Khatami, K Banerjee
Electron Devices Meeting (IEDM), 2013 IEEE International, 2013
Improvement in reliability of tunneling field-effect transistor with pnin structure
W Cao, CJ Yao, GF Jiao, D Huang, HY Yu, MF Li
IEEE transactions on electron devices 58 (7), 2122-2126, 2011
Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects
J Jiang, J Kang, W Cao, X Xie, H Zhang, JH Chu, W Liu, K Banerjee
Nano letters 17 (3), 1482-1488, 2017
Graphene and beyond-graphene 2D crystals for next-generation green electronics
J Kang, W Cao, X Xie, D Sarkar, W Liu, K Banerjee
Micro-and Nanotechnology Sensors, Systems, and Applications VI 9083, 908305, 2014
Subthreshold-swing physics of tunnel field-effect transistors
W Cao, D Sarkar, Y Khatami, J Kang, K Banerjee
AIP Advance 4 (06), 067141-1- 067141-9, 2014
2-D Layered Materials for Next-Generation Electronics: Opportunities and Challenges
W Cao, J Jiang, X Xie, A Pal, JH Chu, J Kang, K Banerje
IEEE Transactions on Electron Devices 65 (10), 4109 - 4121, 2018
Can 2D-nanocrystals extend the lifetime of floating-gate transistor based nonvolatile memory?
W Cao, J Kang, S Bertolazzi, A Kis, K Banerjee
IEEE Transactions on Electron Devices 61 (10), 3456-3464, 2014
Effect of interface traps and oxide charge on drain current degradation in tunneling field-effect transistors
XY Huang, GF Jiao, W Cao, D Huang, HY Yu, ZX Chen, N Singh, GQ Lo, ...
IEEE Electron Device Letters 31 (8), 779-781, 2010
Tilting angle of nanocolumnar films fabricated by oblique angle deposition
H Zhu, W Cao, GK Larsen, R Toole, Y Zhao
Journal of Vacuum Science & Technology B 30 (3), 4, 2012
Performance Evaluation and Design Considerations of 2D Semiconductor based FETs for Sub-10 nm VLSI
W Cao, J Kang, D Sarkar, W Liu, K Banerjee
Electron Devices Meeting (IEDM), 2014 IEEE International, 30.5.1- 30.5.4, 2014
2D electronics: Graphene and beyond
W Cao, J Kang, W Liu, Y Khatami, D Sarkar, B Kaustav
Solid-State Device Research Conference (ESSDERC), 2013 Proceedings of the …, 2013
Designing band-to-band tunneling field-effect transistors with 2D semiconductors for next-generation low-power VLSI
W Cao, J Jiang, J Kang, D Sarkar, W Liu, K Banerjee
2015 IEEE International Electron Devices Meeting (IEDM), 12.3. 1-12.3. 4, 2015
Is negative capacitance FET a steep-slope logic switch?
W Cao, K Banerjee
Nature communications 11 (1), 1-8, 2020
An Ultra-Short Channel Monolayer MoS2 FET Defined By the Curvature of a Thin Nanowire
W Cao, W Liu, J Kang, K Banerjee
IEEE Electron Device Letters 37 (11), 1497 - 1500, 2016
Positive bias temperature instability degradation of InGaAs n-MOSFETs with Al2O3gate dielectric
GF Jiao, W Cao, Y Xuan, DM Huang, PD Ye, MF Li
2011 International Electron Devices Meeting, 27.1. 1-27.1. 4, 2011
Ultimate monolithic-3D integration with 2D materials: rationale, prospects, and challenges
J Jiang, K Parto, W Cao, K Banerjee
IEEE Journal of the Electron Devices Society 7, 878-887, 2019
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Artigos 1–20