Harald Gossner
Harald Gossner
E-mail confirmado em intel.com
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Citado por
A Tunnel FET forScaling Below 0.6 V With a CMOS-Comparable Performance
R Asra, M Shrivastava, KVRM Murali, RK Pandey, H Gossner, VR Rao
IEEE Transactions on Electron Devices 58 (7), 1855-1863, 2011
Insights into the design and optimization of tunnel-FET devices and circuits
A Pal, AB Sachid, H Gossner, VR Rao
IEEE Transactions on Electron Devices 58 (4), 1045-1053, 2011
Simulation methods for ESD protection development
H Gossner, K Esmark, W Stadler
Elsevier, 2003
Physical insight toward heat transport and an improved electrothermal modeling framework for FinFET architectures
M Shrivastava, M Agrawal, S Mahajan, H Gossner, T Schulz, DK Sharma, ...
IEEE Transactions on Electron Devices 59 (5), 1353-1363, 2012
A review on the ESD robustness of drain-extended MOS devices
M Shrivastava, H Gossner
IEEE Transactions on Device and Materials Reliability 12 (4), 615-625, 2012
Operating method for a semiconductor component
K Esmark, H Gossner, P Riess, W Stadler, M Streibl, M Wendel
US Patent 6,905,892, 2005
Semiconductor devices
H Gossner, R Rao, A Sachid, A Pal, R Asra
US Patent 8,405,121, 2013
Field effect transistor with a fin structure
C Russ, H Gossner, T Schulz
US Patent 7,646,046, 2010
Electrostatic discharge protection element
H Gossner, C Russ
US Patent 7,919,816, 2011
Excitonic luminescence from locally grown SiGe wires and dots
J Brunner, TS Rupp, H Gossner, R Ritter, I Eisele, G Abstreiter
Applied physics letters 64 (8), 994-996, 1994
ESD protection element and ESD protection device for use in an electrical circuit
H Gossner, C Russ
US Patent 8,455,949, 2013
Reliability aspects of gate oxide under ESD pulse stress
A Ille, W Stadler, T Pompl, H Gossner, T Brodbeck, K Esmark, P Riess, ...
2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD …, 2007
Vertical Si-metal-oxide-semiconductor field effect transistors with channel lengths of 50 nm by molecular beam epitaxy
H Gossner, I Eisele, L Risch
Japanese journal of applied physics 33 (4S), 2423, 1994
Advanced 2D/3D ESD device simulation-a powerful tool already used in a pre-Si phase
K Esmark, W Stadler, M Wendel, H Gossner, X Guggenmos, W Fichtner
Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 …, 2000
Vertical MOS technology with sub-0.1 µm channel lengths
H Gossner, F Wittmann, I Eisele, T Grabolla, D Behammer
Electronics Letters 31 (16), 1394-1396, 1995
Toward system on chip (SoC) development using FinFET technology: Challenges, solutions, process co-development & optimization guidelines
M Shrivastava, R Mehta, S Gupta, N Agrawal, MS Baghini, DK Sharma, ...
IEEE Transactions on Electron Devices 58 (6), 1597-1607, 2011
MuGFET with increased thermal mass
H Gossner, C Russ, J Schneider, T Schulz
US Patent 7,678,632, 2010
High voltage semiconductor devices
M Shrivastava, MS Baghini, CC Russ, H Gossner, R Rao
US Patent 8,664,720, 2014
Part I: Mixed-signal performance of various high-voltage drain-extended MOS devices
M Shrivastava, MS Baghini, H Gossner, VR Rao
IEEE transactions on electron devices 57 (2), 448-457, 2009
Tunnel-field-effect-transistor based gas-sensor: Introducing gas detection with a quantum-mechanical transducer
D Sarkar, H Gossner, W Hansch, K Banerjee
Applied Physics Letters 102 (2), 023110, 2013
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