Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks N Suda, V Chandra, G Dasika, A Mohanty, Y Ma, S Vrudhula, J Seo, ... Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 535 | 2016 |
Optimizing loop operation and dataflow in FPGA acceleration of deep convolutional neural networks Y Ma, Y Cao, S Vrudhula, J Seo Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 319 | 2017 |
Optimizing the convolution operation to accelerate deep neural networks on FPGA Y Ma, Y Cao, S Vrudhula, J Seo IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (7 …, 2018 | 189 | 2018 |
Scalable and modularized RTL compilation of convolutional neural networks onto FPGA Y Ma, N Suda, Y Cao, J Seo, S Vrudhula 2016 26th International Conference on Field Programmable Logic and …, 2016 | 161 | 2016 |
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks Y Ma, Y Cao, S Vrudhula, J Seo 2017 27th International Conference on Field Programmable Logic and …, 2017 | 112 | 2017 |
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler Y Ma, N Suda, Y Cao, S Vrudhula, J Seo Integration 62, 14-23, 2018 | 75 | 2018 |
End-to-end scalable FPGA accelerator for deep residual networks Y Ma, M Kim, Y Cao, S Vrudhula, J Seo 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 51 | 2017 |
Performance modeling for CNN inference accelerators on FPGA Y Ma, Y Cao, S Vrudhula, JS Seo IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 34 | 2019 |
Automatic compiler based fpga accelerator for cnn training SK Venkataramanaiah, Y Ma, S Yin, E Nurvithadhi, A Dasu, Y Cao, J Seo 2019 29th International Conference on Field Programmable Logic and …, 2019 | 28 | 2019 |
Automatic compilation of diverse CNNs onto high-performance FPGA accelerators Y Ma, Y Cao, S Vrudhula, J Seo IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 27 | 2018 |
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs Y Ma, T Zheng, Y Cao, S Vrudhula, J Seo 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 14 | 2018 |
Efficient network construction through structural plasticity X Du, Z Li, Y Ma, Y Cao IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (3 …, 2019 | 11 | 2019 |
In-memory computing: The next-generation AI computing paradigm Y Ma, Y Du, L Du, J Lin, Z Wang Proceedings of the 2020 on Great Lakes Symposium on VLSI, 265-270, 2020 | 5 | 2020 |
Efficient Hardware Post Processing of Anchor-Based Object Detection on FPGA H Zhang, W Wu, Y Ma, Z Wang 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 580-585, 2020 | 5 | 2020 |
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits Y Ma, M Kim, Y Cao, JS Seo, S Vrudhula 2015 33rd IEEE International Conference on Computer Design (ICCD), 443-446, 2015 | 3 | 2015 |
An Efficient FPGA Accelerator Optimized for High Throughput Sparse CNN Inference J Wen, Y Ma, Z Wang 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 165-168, 2020 | 2 | 2020 |
Small-world-based structural pruning for efficient FPGA inference of deep neural networks G Krishnan, Y Ma, Y Cao 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit …, 2020 | 1 | 2020 |
Optimizing stochastic computing for low latency inference of convolutional neural networks Z Chen, Y Ma, Z Wang Proceedings of the 39th International Conference on Computer-Aided Design, 1-7, 2020 | 1 | 2020 |
Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA X Wu, Y Ma, Z Wang 2020 IEEE 33rd International System-on-Chip Conference (SOCC), 168-173, 2020 | 1 | 2020 |
Hardware Acceleration of Deep Convolutional Neural Networks on FPGA Y Ma Arizona State University, 2018 | 1 | 2018 |