Qian Ge

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Gernot HeiserProfessor of Computer Science, University of New South WalesVerified email at unsw.edu.au
Yuval YaromRuhr University BochumVerified email at rub.de
Ruby B. LeeForrest G. Hamrick Professor of Electrical Engineering, also Computer ScienceVerified email at princeton.edu
Fangfei LiuIntel CorporationVerified email at intel.com
David CockSenior Researcher, ETH ZurichVerified email at cse.unsw.edu.au
Carlos V RozasIntel LabsVerified email at intel.com
Frank McKeenIntel CorpVerified email at mckeen.us
Toby MurraySchool of Computing and Information Systems, University of MelbourneVerified email at unimelb.edu.au
Tom ChothiaUniversity of BirminghamVerified email at cs.bham.ac.uk

Qian Ge

Verified email at google.com


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
Last-level cache side-channel attacks are practical F Liu, Y Yarom, Q Ge, G Heiser, RB Lee IEEE Symposium on Security and Privacy (S&P), 605-622, 2015	1411	2015
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware Q Ge, Y Yarom, D Cock, G Heiser Journal of Cryptographic Engineering 8 (1), 1 - 27, 2018	520	2018
CATalyst: defeating last-level cache side channel attacks in cloud computing GHRBL Fangfei Liu, Qian Ge, Yuval Yarom, Frank Mckeen, Carlos Rozas IEEE Symposium on High-Performance Computer Architecture, 2016	520*	2016
Mapping the Intel Last-Level Cache Y Yarom, Q Ge, F Liu, RB Lee, G Heiser IACR Cryptology ePrint Archive 2015, 905, 2015	142	2015
The last mile: An empirical study of timing channels on seL4 D Cock, Q Ge, T Murray, G Heiser Proceedings of the 2014 ACM SIGSAC Conference on Computer and Communications …, 2014	122	2014
Time protection: the missing OS abstraction Q Ge, Y Yarom, T Chothia, G Heiser Eurosys2019, 2019	96	2019
No Security Without Time Protection: We Need a New Hardware-Software Contract Q Ge, Y Yarom, G Heiser APSys 2018, 2018	56	2018
Your Processor Leaks Information - and There's Nothing You Can Do About It Q Ge, Y Yarom, F Li, G Heiser https://arxiv.org/abs/1612.04474, 2017	36*	2017
Principled Elimination of Microarchitectural Timing Channels through Operating-System Enforced Time Protection Q Ge University of New South Wales Sydney, Australia, 2019	4	2019

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